8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 40.680s | 33.672ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 15.790s | 6.907ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 14.890s | 7.484ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.040s | 2.406ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 15.440s | 17.787ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.030s | 2.118ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 14.890s | 7.484ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 15.440s | 17.787ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 15.630s | 2.147ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 16.120s | 8.633ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.970s | 8.586ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.706m | 9.392ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.540s | 8.054ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.970s | 21.197ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 21.680s | 8.479ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 21.680s | 8.479ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 15.790s | 6.907ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 14.890s | 7.484ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 15.440s | 17.787ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.450s | 8.669ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 15.790s | 6.907ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 14.890s | 7.484ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 15.440s | 17.787ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 17.450s | 8.669ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.594m | 25.166ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.711m | 708.335us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.334m | 8.288ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.711m | 708.335us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.711m | 708.335us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.711m | 708.335us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 40.680s | 33.672ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 40.680s | 33.672ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 40.680s | 33.672ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.334m | 8.288ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 34.540s | 8.054ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.094m | 48.089ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.594m | 25.166ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.711m | 708.335us | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.733h | 68.414ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 466 | 500 | 93.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.43 | 97.04 | 92.65 | 97.88 | 100.00 | 98.37 | 97.89 | 98.14 |
UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.rom_ctrl_stress_all_with_rand_reset.68816168569313800427136051067770598457571170266238307626567478691028690551657
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3549031957 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3549031957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rom_ctrl_stress_all_with_rand_reset.106092600922201766130419802731391532977854694985660913415817569468225957747342
Line 590, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 174361721197 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 174361721197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
1.rom_ctrl_stress_all_with_rand_reset.100729198589039690936437572229793709045391846205857854978571060805669934336560
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:24c5fb61-06cd-435b-8066-2cddc208a542
4.rom_ctrl_stress_all_with_rand_reset.74324058778360295513472410568933125243793997278251317371280012059105347331332
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:adbd953b-637b-42b6-9842-3fb9a5e10d2a
... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
17.rom_ctrl_stress_all_with_rand_reset.29352806977398433944287658325944881295290305182661083760314459224702939575496
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10014113502 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9334e52b
UVM_INFO @ 10014113502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rom_ctrl_stress_all_with_rand_reset.92035189275183402634235125109032545632467227780056954591047668498013117777375
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10010817980 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1aecbf2a
UVM_INFO @ 10010817980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
11.rom_ctrl_corrupt_sig_fatal_chk.46886722091600910757099836694830434058170905652845423543930418556273636177314
Line 278, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 15400693050 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 15400693050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
47.rom_ctrl_stress_all_with_rand_reset.66565965191397606187056319167316465627061123049487961438081901723810310226733
Line 412, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 224343661678 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 224343661678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---