ROM_CTRL Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.690s	77.724ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.360s	3.401ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.850s	2.163ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.400s	1.849ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.200s	3.509ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.560s	2.125ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.850s	2.163ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.200s	3.509ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.570s	4.110ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.860s	8.516ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.720s	2.108ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.335m	8.361ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.770s	15.989ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.850s	2.097ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.270s	10.990ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.270s	10.990ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.360s	3.401ms	5	5	100.00
		rom_ctrl_csr_rw	15.850s	2.163ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.200s	3.509ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.620s	1.963ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.360s	3.401ms	5	5	100.00
		rom_ctrl_csr_rw	15.850s	2.163ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.200s	3.509ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.620s	1.963ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.581m	12.158ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.761m	7.458ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.351m	2.386ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.761m	7.458ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.761m	7.458ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.761m	7.458ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.690s	77.724ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.690s	77.724ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.690s	77.724ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.351m	2.386ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.770s	15.989ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.226m	181.026ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.581m	12.158ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.761m	7.458ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.002h	79.755ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	97.04	92.65	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.38790766813892243924703428306321972542119525969625116340135329969929146440952
    Line 490, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30711828324 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30711828324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.91922300413190136931696261178544226519375781034681502191101083134185384500938
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107810038 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107810038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 21.rom_ctrl_stress_all_with_rand_reset.93296543933940732464930346415835592849864736166696019285702327930733431523739
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e77b97f0-2c15-471c-92f8-4aba3ef5b4f6
```
  - 27.rom_ctrl_stress_all_with_rand_reset.45386447906149129566936526971459634600697306516550594994014575041035643257193
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6875c24b-b746-40a6-8d4c-b8e6d3b25ca5
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.14501224798000682018961065196417471807642317382143828282718173318455172056963
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006722819 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3df9ec2a
  UVM_INFO @ 10006722819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rom_ctrl_stress_all_with_rand_reset.71312672553853185733216686886040417433565643285709898068460264042437696420974
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13411603522 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf52126a4
  UVM_INFO @ 13411603522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 23.rom_ctrl_stress_all.55926495993330217607454572972370329522849311099049064950790213855069747094849
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 1715832343 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1715832343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `bc285b7382`