ROM_CTRL/64KB Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.265m	7.867ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	40.820s	60.693ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.800s	8.226ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.360s	13.631ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.270s	4.221ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	28.300s	56.267ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.800s	8.226ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.270s	4.221ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	22.240s	4.968ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	25.630s	5.854ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.500s	77.589ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	5.108m	106.815ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.190m	8.462ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.450s	4.104ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.600s	16.539ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.600s	16.539ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	40.820s	60.693ms	5	5	100.00
		rom_ctrl_csr_rw	31.800s	8.226ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.270s	4.221ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.730s	22.428ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	40.820s	60.693ms	5	5	100.00
		rom_ctrl_csr_rw	31.800s	8.226ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.270s	4.221ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.730s	22.428ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.264m	51.271ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.262m	5.337ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.847m	17.566ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.262m	5.337ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.262m	5.337ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.262m	5.337ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.265m	7.867ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.265m	7.867ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.265m	7.867ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.847m	17.566ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.190m	8.462ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	16.776m	344.498ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.264m	51.271ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.262m	5.337ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.211h	96.091ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			458	500	91.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.97	93.25	97.88	100.00	99.01	97.89	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.31284457412770523644837767637621844457042151895339803891291571065425669425699
    Line 384, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22236054664 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22236054664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.46001499125284152406539807049651218461812006181694883001062605465880522469747
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1274686008 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1274686008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.34804230317171698029183408281885229541069984817784745301850372867138033415387
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10548446411 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xadf3864f
  UVM_INFO @ 10548446411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.50433892328528120957985270345517307377253537822883668064736266384373259948217
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10534523334 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x51e68e69
  UVM_INFO @ 10534523334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.26970338244902083560081142369819378885242789373025193244517141987151052268223
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bf222a93-a403-4564-b479-ab55a331245b
```
  - 5.rom_ctrl_stress_all_with_rand_reset.99029204164187951346544989773548695756210781744528385859841954523039010471447
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3f1afd34-20bc-4e97-8b62-8fa6404fd45f
```
  - ... and 6 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 5.rom_ctrl_stress_all.66084724837287208611708257320359402670505570669112330533339166429318762204402
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 3590603352 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3590603352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.106425521388303104030625292104903752722704775625790942178812926524562061795866
    Line 645, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 707238368447 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 707238368447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c187a82ee8`