ROM_CTRL/32KB Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 43.880s 4.068ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 36.880s 41.555ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 31.720s 4.873ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 27.940s 3.226ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 29.380s 14.167ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 32.520s 16.786ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 31.720s 4.873ms 20 20 100.00
rom_ctrl_csr_aliasing 29.380s 14.167ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 22.680s 8.273ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 27.160s 6.605ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 17.960s 3.468ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.544m 8.642ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 35.090s 4.257ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 16.460s 8.278ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 38.720s 17.981ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 38.720s 17.981ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 36.880s 41.555ms 5 5 100.00
rom_ctrl_csr_rw 31.720s 4.873ms 20 20 100.00
rom_ctrl_csr_aliasing 29.380s 14.167ms 5 5 100.00
rom_ctrl_same_csr_outstanding 35.330s 35.121ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 36.880s 41.555ms 5 5 100.00
rom_ctrl_csr_rw 31.720s 4.873ms 20 20 100.00
rom_ctrl_csr_aliasing 29.380s 14.167ms 5 5 100.00
rom_ctrl_same_csr_outstanding 35.330s 35.121ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 3.219m 98.406ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.828m 22.546ms 5 5 100.00
rom_ctrl_tl_intg_err 2.933m 9.074ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.828m 22.546ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.828m 22.546ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.828m 22.546ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 43.880s 4.068ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 43.880s 4.068ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 43.880s 4.068ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.933m 9.074ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
rom_ctrl_kmac_err_chk 35.090s 4.257ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 9.849m 61.540ms 49 50 98.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 3.219m 98.406ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.828m 22.546ms 5 5 100.00
V2S TOTAL 94 95 98.95
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.702h 725.715ms 14 50 28.00
V3 TOTAL 14 50 28.00
TOTAL 463 500 92.60

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 3 75.00
V3 1 1 0 0.00

Failure Buckets

Past Results