ROM_CTRL/64KB Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	46.080s	17.154ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	31.870s	27.318ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.050s	10.276ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.470s	4.067ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	25.480s	3.028ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.920s	4.277ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.050s	10.276ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.480s	3.028ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	28.460s	4.583ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.400s	21.218ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.550s	23.793ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.079m	14.411ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.380s	17.167ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	17.040s	4.263ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	34.400s	19.770ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	34.400s	19.770ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	31.870s	27.318ms	5	5	100.00
		rom_ctrl_csr_rw	32.050s	10.276ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.480s	3.028ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	29.410s	12.602ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	31.870s	27.318ms	5	5	100.00
		rom_ctrl_csr_rw	32.050s	10.276ms	20	20	100.00
		rom_ctrl_csr_aliasing	25.480s	3.028ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	29.410s	12.602ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.224m	96.286ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.752m	413.586us	5	5	100.00
		rom_ctrl_tl_intg_err	2.884m	14.434ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.752m	413.586us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.752m	413.586us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.752m	413.586us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	46.080s	17.154ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	46.080s	17.154ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	46.080s	17.154ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.884m	14.434ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.380s	17.167ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.488m	433.219ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.224m	96.286ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.752m	413.586us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.844h	30.321ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.65	96.97	93.25	97.88	100.00	99.01	98.04	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.52716212780450146090599369898386036627092993054928026931777917051794133384857
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 393095925 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 393095925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.99032527986682472957300498245530994411464938372547679469410855463480542077897
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 124326395 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 124326395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.71406597031458421325996408517928104329695395118479877726457923220952514545645
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2339de95-ac41-4ce8-842e-683679ff1737
```
  - 18.rom_ctrl_stress_all_with_rand_reset.22846049338623348027080922755950137422829435860436220348623621899950753845087
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:56881a39-7101-498a-aed1-8c43fb1fe1b7
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.21427289326662540621656029459834754874301585103982304761595225533196475184434
    Line 490, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 454590779430 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 454590779430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 42.rom_ctrl_kmac_err_chk.87244150965361801044338813303584208972610318659577562352198069609546838901257
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/42.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3315132804 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3315132804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 26.rom_ctrl_stress_all_with_rand_reset.110407018636474598050145208783850561814189096998879591677233662575010327680843
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11420317746 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x71a5a2d5
  UVM_INFO @ 11420317746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.rom_ctrl_stress_all_with_rand_reset.91833449066568090458314773735347185802908415029148932798658370162486046759991
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10016640379 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x325d4478
  UVM_INFO @ 10016640379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f7fc348358`