4ee21f808f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.598m | 34.143ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 38.630s | 4.107ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 31.920s | 4.346ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 21.790s | 4.108ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 28.160s | 3.542ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 34.010s | 15.707ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 31.920s | 4.346ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 28.160s | 3.542ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 21.710s | 6.906ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 25.680s | 11.836ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.210s | 38.911ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 6.094m | 189.779ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.188m | 17.473ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 32.180s | 4.145ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 37.280s | 4.294ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 37.280s | 4.294ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 38.630s | 4.107ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.920s | 4.346ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 28.160s | 3.542ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 37.190s | 26.106ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 38.630s | 4.107ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.920s | 4.346ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 28.160s | 3.542ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 37.190s | 26.106ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 2.944m | 21.667ms | 18 | 20 | 90.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.783m | 5.436ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.966m | 3.306ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.783m | 5.436ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.783m | 5.436ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.783m | 5.436ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.598m | 34.143ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.598m | 34.143ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.598m | 34.143ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.966m | 3.306ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 1.188m | 17.473ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 18.697m | 118.570ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 2.944m | 21.667ms | 18 | 20 | 90.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.783m | 5.436ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 93 | 95 | 97.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.252h | 130.383ms | 7 | 50 | 14.00 |
| V3 | TOTAL | 7 | 50 | 14.00 | |||
| TOTAL | 455 | 500 | 91.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
0.rom_ctrl_stress_all_with_rand_reset.32001957092400036636108940254893198141330547105172780181767938736061421898540
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1509603042 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1509603042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.94119374650897135014876901864781024147669621453825895305183415640235728187363
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 227123393 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 227123393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 10 failures:
5.rom_ctrl_stress_all_with_rand_reset.66483134962403910695905234142471480276633569106175367772587773045613839875027
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003693644 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2884a0fd
UVM_INFO @ 10003693644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rom_ctrl_stress_all_with_rand_reset.102413735300696798489755304346093568955205627231411676141579353011045068507094
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10943635324 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3d4bc268
UVM_INFO @ 10943635324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
7.rom_ctrl_stress_all_with_rand_reset.14773018976821878902641190222437635296960262735199881371415285666162621769468
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:54f427f0-acd3-438a-8165-060368efa856
20.rom_ctrl_stress_all_with_rand_reset.49070808854005501403561973627539725128182738415180665557106691563358316489704
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a4c868b0-cb35-4238-b2da-31726931ac7a
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
11.rom_ctrl_passthru_mem_tl_intg_err.43025498696479629199023850502355753802015991442861718324448743481124282154600
Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rom_ctrl_passthru_mem_tl_intg_err.94209572422421262412767693767324543564095784412723103607769099549228150667094
Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rom_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log
Job ID: smart:bda2f6bd-7392-44ee-b81f-d2d427c61bce