ROM_CTRL/64KB Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.010s	6.630ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.650s	13.228ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.510s	3.902ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.610s	7.374ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.040s	1.946ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.520s	11.516ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.510s	3.902ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.040s	1.946ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.480s	7.046ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.610s	8.042ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.710s	2.179ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.213m	160.497ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.670s	4.316ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.230s	2.441ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.350s	2.074ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.350s	2.074ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.650s	13.228ms	5	5	100.00
		rom_ctrl_csr_rw	15.510s	3.902ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.040s	1.946ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.650s	7.297ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.650s	13.228ms	5	5	100.00
		rom_ctrl_csr_rw	15.510s	3.902ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.040s	1.946ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.650s	7.297ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.733m	176.317ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.779m	6.225ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.250m	5.132ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.779m	6.225ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.779m	6.225ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.779m	6.225ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.010s	6.630ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.010s	6.630ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.010s	6.630ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.250m	5.132ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.670s	4.316ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	11.137m	70.693ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.733m	176.317ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.779m	6.225ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.273h	37.167ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.96	93.40	97.88	100.00	98.68	98.04	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.34969296150508051590586019607953460924223378388838993216518452611146928753875
    Line 275, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3939224692 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3939224692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.89397900268694272846821685877051166672398364588092091288892850279772491365720
    Line 582, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37166772519 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 37166772519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.65237782279579252319882411034393584451101864919338541114794215784490036789619
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5abb5cf1-e370-45cc-ad61-b2e1e249c8cd
```
  - 9.rom_ctrl_stress_all_with_rand_reset.63801195616627748244484885317404604688729205440250473673182176128320210160656
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0da28ee4-35e2-45a5-bcaf-062ff425caff
```
  - ... and 9 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test rom_ctrl_smoke has 1 failures.

1.rom_ctrl_smoke.31120038298955403968918425695883055885648454450492516061079968573458527031966
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log

  [make]: simulate
  cd /workspace/1.rom_ctrl_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583092382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1583092382
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Mar 31 12:28 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 43.rom_ctrl_smoke.74765187646784495970430299280330232520654235278070804302772455855974117513821
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/43.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017738934 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb74b24c9
  UVM_INFO @ 40017738934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.rom_ctrl_stress_all_with_rand_reset.9344072693167408717947216476808182970013111232781598991438374150416745852162
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11544360581 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd512c596
  UVM_INFO @ 11544360581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```