ROM_CTRL/32KB Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.290s	17.745ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.120s	1.634ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.680s	7.864ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.900s	6.500ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.870s	4.123ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.020s	1.422ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.680s	7.864ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.870s	4.123ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.090s	7.691ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.350s	5.712ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.710s	2.407ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.094m	13.350ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.120s	30.529ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.600s	21.417ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.620s	4.093ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.620s	4.093ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.120s	1.634ms	5	5	100.00
		rom_ctrl_csr_rw	15.680s	7.864ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.870s	4.123ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.180s	23.390ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.120s	1.634ms	5	5	100.00
		rom_ctrl_csr_rw	15.680s	7.864ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.870s	4.123ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.180s	23.390ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.624m	51.315ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.779m	29.856ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.290m	1.838ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.779m	29.856ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.779m	29.856ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.779m	29.856ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.290s	17.745ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.290s	17.745ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.290s	17.745ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.290m	1.838ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.120s	30.529ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.530m	46.563ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.624m	51.315ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.779m	29.856ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.789h	253.530ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.96	93.40	97.88	100.00	98.68	98.04	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.40129455025060900111283310432036240906751315328219284751755016664627594674280
    Line 378, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24712666152 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24712666152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.113277358462177746010077295980242037910883851400987610619450667524028356894148
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 861183288 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 861183288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.47266694242806157680407854537050885692825779972154828650503994191445438461232
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cb964925-41ed-43c5-9dee-04d7aef41863
```
  - 8.rom_ctrl_stress_all_with_rand_reset.36704622944323378960236861072442119479874469191195747161501530326136039801814
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8141538c-0050-48c4-89fc-dde838d3963a
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.103100225306170260426371317992258912093372640544306191259941654062775718107535
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10008553706 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x8380c3dc
  UVM_INFO @ 10008553706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_stress_all_with_rand_reset.100654406427449606768287463118561354866995522001452830671273494950558405743494
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12005445000 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb9af470b
  UVM_INFO @ 12005445000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 28.rom_ctrl_stress_all.47191360575481257100501302757459829729949847887068516445706917765606303354992
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 79802074925 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x78b13411
  UVM_INFO @ 79802074925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `919341eb22`