Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 u_compare


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
0.00 0.00
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr

TotalCoveredPercent
Totals 6 0 0.00
Total Bits 20 0 0.00
Total Bits 0->1 10 0 0.00
Total Bits 1->0 10 0 0.00

Ports 6 0 0.00
Port Bits 20 0 0.00
Port Bits 0->1 10 0 0.00
Port Bits 1->0 10 0 0.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i No No No INPUT
rst_ni No No No INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i No No No INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] No No No OUTPUT
cnt_after_commit_o[2:0] No No No OUTPUT
err_o No No No OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
0.00 0.00
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
0.00 0.00
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

TotalCoveredPercent
Totals 8 0 0.00
Total Bits 20 0 0.00
Total Bits 0->1 10 0 0.00
Total Bits 1->0 10 0 0.00

Ports 8 0 0.00
Port Bits 20 0 0.00
Port Bits 0->1 10 0 0.00
Port Bits 1->0 10 0 0.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i No No No INPUT
rst_ni No No No INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i No No No INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] No No No INPUT
incr_en_i No No No INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] No No No OUTPUT
cnt_after_commit_o[1:0] No No No OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
Toggle Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr