Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_compare
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare 0.00 0.00 0.00 0.00 0.00


Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 gen_fsm_scramble_enabled.u_checker_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_done_sender 0.00 0.00 0.00
u_prim_count_addr 0.00 0.00
u_state_regs 0.00 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_compare
Line No.TotalCoveredPercent
TOTAL2400.00
ALWAYS85300.00
ALWAYS88700.00
CONT_ASSIGN108100.00
CONT_ASSIGN114100.00
CONT_ASSIGN120100.00
CONT_ASSIGN125100.00
CONT_ASSIGN148100.00
CONT_ASSIGN149100.00
CONT_ASSIGN150100.00
CONT_ASSIGN152100.00
ALWAYS154400.00
CONT_ASSIGN163100.00
CONT_ASSIGN177100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 0 3
88 0 1
89 0 1
90 0 1
92 0 2
==> MISSING_ELSE
95 0 2
==> MISSING_ELSE
108 0 1
114 0 1
120 0 1
125 0 1
148 0 1
149 0 1
150 0 1
152 0 1
154 0 1
155 0 1
157 0 1
158 0 1
==> MISSING_ELSE
163 0 1
177 0 1

Cond Coverage for Module : rom_ctrl_compare
TotalCoveredPercent
Conditions4300.00
Logical4300.00
Non-Logical00
Event00

 LINE       95
 EXPRESSION (addr_q == LastAddr)
            ----------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       108
 EXPRESSION (start_i && (state_q != Waiting))
             ---1---    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       108
 SUB-EXPRESSION (state_q != Waiting)
                ----------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 EXPRESSION ((state_q == Waiting) && (addr_q != '0))
             ----------1---------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       114
 SUB-EXPRESSION (state_q == Waiting)
                ----------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       114
 SUB-EXPRESSION (addr_q != '0)
                -------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       120
 EXPRESSION ((state_q == Done) && (addr_q != LastAddr))
             --------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       120
 SUB-EXPRESSION (state_q == Done)
                --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       120
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       125
 EXPRESSION ((state_q == Checking) && (addr_q != LastAddr))
             ----------1----------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       125
 SUB-EXPRESSION (state_q == Checking)
                ----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       125
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       152
 EXPRESSION (matches_q && (digest_word == exp_digest_word))
             ----1----    ----------------2---------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       152
 SUB-EXPRESSION (digest_word == exp_digest_word)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       157
 EXPRESSION (state_q == Checking)
            ----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       163
 EXPRESSION (state_q == Done)
            --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       177
 EXPRESSION (fsm_alert | start_alert | wait_addr_alert | done_addr_alert | addr_ctr_alert)
             ----1----   -----2-----   -------3-------   -------4-------   -------5------
-1--2--3--4--5-StatusTests
00000Not Covered
00001Not Covered
00010Not Covered
00100Not Covered
01000Not Covered
10000Not Covered
FSM Coverage for Module : rom_ctrl_compare
Summary for FSM :: state_q
TotalCoveredPercent
States 3 0 0.00 (Not included in score)
Transitions 2 0 0.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Checking 92 Not Covered
Done 95 Not Covered
Waiting 91 Not Covered


transitionsLine No.CoveredTests
Checking->Done 95 Not Covered
Waiting->Checking 92 Not Covered


Branch Coverage for Module : rom_ctrl_compare
Line No.TotalCoveredPercent
Branches 11 0 0.00
IF 85 2 0 0.00
CASE 90 6 0 0.00
IF 154 3 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	90	case (state_q)
-2-:	92	if (start_i)
-3-:	95	if ((addr_q == LastAddr))

Branches:
-1--2--3-StatusTests
Waiting 1 - Not Covered
Waiting 0 - Not Covered
Checking - 1 Not Covered
Checking - 0 Not Covered
Done - - Not Covered
default - - Not Covered 



	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	157	if ((state_q == Checking))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered

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