Unified Coverage Report :: Module :: rom_ctrl_counter

Module : rom_ctrl_counter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_fsm_scramble_enabled.u_checker_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_counter

	Line No.	Total	Covered	Percent
TOTAL		23	0	0.00
CONT_ASSIGN	74	1	0	0.00
ALWAYS	76	3	0	0.00
ALWAYS	84	6	0	0.00
ALWAYS	94	5	0	0.00
CONT_ASSIGN	108	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	113	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	117	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	0	1
76	0	1
77	0	1
79	0	1
84	0	1
85	0	1
86	0	1
87	0	1
88	0	1
89	0	1
			==> MISSING_ELSE
94	0	1
95	0	1
96	0	1
101	0	1
104	0	1
108	0	1
110	0	1
111	0	1
113	0	1
114	0	1
115	0	1
116	0	1
117	0	1

---

Cond Coverage for Module : rom_ctrl_counter

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (addr_q == TopAddr)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       108
 EXPRESSION (data_rdy_i & vld_q & ((~done_d)))
             -----1----   --2--   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       111
 EXPRESSION (addr_q == TNTAddr)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       114
 EXPRESSION (go ? addr_d : addr_q)
             -1

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : rom_ctrl_counter

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	114	2	0	0.00
IF	76	2	0	0.00
IF	84	3	0	0.00
IF	94	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	114	(go) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	76	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	84	if ((!rst_ni))
-2-:	87	if (go)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	94	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered