Unified Coverage Report :: Module :: rom_ctrl_fsm

Module : rom_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
24.25	0.00	0.00	97.02		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_compare	0.00	0.00	0.00	0.00	0.00	0.00
u_counter	0.00	0.00	0.00			0.00
u_state_regs	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		58	0	0.00
ALWAYS	138	3	0	0.00
ALWAYS	141	19	0	0.00
ALWAYS	209	3	0	0.00
CONT_ASSIGN	216	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	220	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	232	1	0	0.00
CONT_ASSIGN	233	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
ALWAYS	261	5	0	0.00
ALWAYS	270	3	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
ALWAYS	288	3	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	312	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	3
141	0	1
142	0	1
144	0	1
148	0	1
149	0	1
			==> MISSING_ELSE
154	0	1
155	0	1
156	0	1
157	0	1
163	0	2
			==> MISSING_ELSE
167	0	2
			==> MISSING_ELSE
171	0	2
			==> MISSING_ELSE
194	0	1
197	0	1
			==> MISSING_ELSE
203	0	1
204	0	1
			==> MISSING_ELSE
209	0	3
216	0	1
217	0	1
220	0	1
223	0	1
224	0	1
231	0	1
232	0	1
233	0	1
239	0	1
241	0	1
242	0	1
243	0	1
247	0	1
251	0	1
261	0	1
262	0	1
263	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
277	0	1
278	0	1
279	0	1
288	0	1
289	0	1
291	0	1
304	0	1
307	0	1
309	0	1
310	0	1
312	0	1

---

Cond Coverage for Module : rom_ctrl_fsm

	Total	Covered	Percent
Conditions	55	0	0.00
Logical	55	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       148
 EXPRESSION (counter_lnt && kmac_rom_rdy_i && kmac_rom_vld_o)
             -----1-----    -------2------    -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       156
 EXPRESSION (kmac_err_i ? Invalid : KmacAhead)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       157
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       163
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 EXPRESSION 
 Number  Term
      1  (checker_done && ((!(state_q inside {Checking, Done})))) || 
      2  (counter_done && (state_q == ReadingLow)) || 
      3  (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead})))))

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       194
 SUB-EXPRESSION (checker_done && ((!(state_q inside {Checking, Done}))))
                 ------1-----    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       194
 SUB-EXPRESSION (counter_done && (state_q == ReadingLow))
                 ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       194
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 SUB-EXPRESSION (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead}))))
                 -----1-----    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION (((state_q == ReadingHigh) || (state_q == KmacAhead)) & ((~counter_done)))
             --------------------------1-------------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 SUB-EXPRESSION ((state_q == ReadingHigh) || (state_q == KmacAhead))
                 ------------1-----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       231
 SUB-EXPRESSION (state_q == ReadingHigh)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 SUB-EXPRESSION (state_q == KmacAhead)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       265
 EXPRESSION (counter_read_req && (state_q == ReadingLow) && ((!counter_lnt)))
             --------1-------    -----------2-----------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       265
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (kmac_rom_rdy_i | (state_q inside {ReadingHigh, KmacAhead}))
             -------1------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       291
 EXPRESSION ((state_q != Checking) && (state_d == Checking))
             ----------1----------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       291
 SUB-EXPRESSION (state_q != Checking)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       291
 SUB-EXPRESSION (state_d == Checking)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       312
 EXPRESSION (fsm_alert | checker_alert | unexpected_counter_change)
             ----1----   ------2------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

FSM Coverage for Module : rom_ctrl_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Checking	157	Not Covered
Done	171	Not Covered
Invalid	156	Not Covered
KmacAhead	156	Not Covered
ReadingHigh	149	Not Covered
ReadingLow	145	Not Covered
RomAhead	155	Not Covered

transitions	Line No.	Covered	Tests
Checking->Done	171	Not Covered
Checking->Invalid	197	Not Covered
Done->Invalid	197	Not Covered
KmacAhead->Checking	167	Not Covered
KmacAhead->Invalid	197	Not Covered
ReadingHigh->Checking	157	Not Covered
ReadingHigh->Invalid	156	Not Covered
ReadingHigh->KmacAhead	156	Not Covered
ReadingHigh->RomAhead	155	Not Covered
ReadingLow->Invalid	197	Not Covered
ReadingLow->ReadingHigh	149	Not Covered
RomAhead->Checking	163	Not Covered
RomAhead->Invalid	163	Not Covered

---

Branch Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		33	0	0.00
IF	138	2	0	0.00
CASE	144	17	0	0.00
IF	194	2	0	0.00
IF	203	2	0	0.00
IF	209	2	0	0.00
IF	262	2	0	0.00
IF	265	2	0	0.00
IF	270	2	0	0.00
IF	288	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	148	if (((counter_lnt && kmac_rom_rdy_i) && kmac_rom_vld_o))
-3-:	154	case ({kmac_done_i, counter_done})
-4-:	156	(kmac_err_i) ? 
-5-:	157	(kmac_err_i) ? 
-6-:	163	if (kmac_done_i)
-7-:	163	(kmac_err_i) ? 
-8-:	167	if (counter_done)
-9-:	171	if (checker_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ReadingLow	1	-	-	-	-	-	-	-	Not Covered
ReadingLow	0	-	-	-	-	-	-	-	Not Covered
ReadingHigh	-	2'b01	-	-	-	-	-	-	Not Covered
ReadingHigh	-	2'b10	1	-	-	-	-	-	Not Covered
ReadingHigh	-	2'b10	0	-	-	-	-	-	Not Covered
ReadingHigh	-	2'b11	-	1	-	-	-	-	Not Covered
ReadingHigh	-	2'b11	-	0	-	-	-	-	Not Covered
ReadingHigh	-	default	-	-	-	-	-	-	Not Covered
RomAhead	-	-	-	-	1	1	-	-	Not Covered
RomAhead	-	-	-	-	1	0	-	-	Not Covered
RomAhead	-	-	-	-	0	-	-	-	Not Covered
KmacAhead	-	-	-	-	-	-	1	-	Not Covered
KmacAhead	-	-	-	-	-	-	0	-	Not Covered
Checking	-	-	-	-	-	-	-	1	Not Covered
Checking	-	-	-	-	-	-	-	0	Not Covered
Done	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	194	if ((((checker_done && (!(state_q inside {Checking, Done}))) || (counter_done && (state_q == ReadingLow))) || (kmac_done_i && (!(state_q inside {ReadingHigh, RomAhead})))))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	203	if (alert_o)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	209	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	262	if (kmac_rom_rdy_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	265	if (((counter_read_req && (state_q == ReadingLow)) && (!counter_lnt)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	270	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered