Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_adapter_rom	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_tl_adapter_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
22.69	0.00	0.00	90.74		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
24.25	0.00	0.00	97.02		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	50.00	0.00		100.00
u_err	0.00	0.00	0.00			0.00
u_reqfifo	0.00	0.00	0.00			0.00
u_rsp_gen	0.00	0.00
u_rspfifo	0.00	0.00	0.00	0.00		0.00
u_sram_byte	0.00	0.00
u_sramreqfifo	0.00	0.00	0.00			0.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		65	0	0.00
ALWAYS	93	4	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	107	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	119	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
ALWAYS	229	8	0	0.00
ALWAYS	249	6	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	297	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
CONT_ASSIGN	322	1	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
ALWAYS	354	6	0	0.00
ALWAYS	366	5	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	378	1	0	0.00
CONT_ASSIGN	387	1	0	0.00
CONT_ASSIGN	388	1	0	0.00
CONT_ASSIGN	390	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	398	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	405	1	0	0.00
CONT_ASSIGN	406	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
ALWAYS	421	3	0	0.00
CONT_ASSIGN	442	1	0	0.00
CONT_ASSIGN	447	1	0	0.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	0	1
94	0	1
95	0	1
96	0	1
			==> MISSING_ELSE
102	0	1
107	0	1
114	0	1
119	0	1
139	0	1
151	0	1
222	0	1
223	0	1
224	0	1
229	0	1
231	0	1
232	0	1
234	0	1
235	0	1
236	0	1
239	0	1
242	0	1
249	0	1
251	0	1
252	0	1
253	0	1
255	0	1
258	0	1
263	0	1
267	0	1
286	0	1
291	0	1
297	0	1
301	0	1
321	0	1
322	0	1
323	0	1
324	0	1
354	0	1
355	0	1
357	0	1
358	0	1
359	0	1
360	0	1
			==> MISSING_ELSE
366	0	1
367	0	1
369	0	1
370	0	1
371	0	1
			==> MISSING_ELSE
377	0	1
378	0	1
387	0	1
388	0	1
390	0	1
391	0	1
398	0	1
401	0	1
405	0	1
406	0	1
408	0	1
415	0	1
421	0	1
425	0	1
427	0	1
			==> MISSING_ELSE
442	0	1
447	0	1
452		unreachable

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	118	0	0.00
Logical	118	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		27	0	0.00
TERNARY	107	2	0	0.00
TERNARY	291	2	0	0.00
TERNARY	297	3	0	0.00
TERNARY	324	2	0	0.00
TERNARY	447	2	0	0.00
IF	93	3	0	0.00
IF	231	4	0	0.00
IF	251	3	0	0.00
IF	357	2	0	0.00
IF	369	2	0	0.00
IF	425	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Not Covered

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	425	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered