Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
24.25	0.00	0.00	97.02		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	24.25	0.00	0.00	97.02		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
24.25	0.00	0.00	97.02		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.54	39.18	35.44	91.88	0.00	44.08	98.63

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	0.00	0.00	0.00	0.00	0.00	0.00
gen_rom_scramble_enabled.u_rom	0.00	0.00		0.00		0.00
regs_tlul_assert_device	33.33	0.00				0.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	32.40	0.00				0.00	97.20
u_mux	0.00	0.00	0.00			0.00
u_reg_regs	98.63	99.11	98.02	97.51		98.53	100.00
u_tl_adapter_rom	22.69	0.00	0.00	90.74		0.00
u_tl_rom_h2d_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	127	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	207	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	425	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	427	1	0	0.00
CONT_ASSIGN	428	1	0	0.00
CONT_ASSIGN	433	1	0	0.00
CONT_ASSIGN	437	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	0	1
125	0	1
126	0	1
127	0	1
128	0	1
131	0	1
207	0	1
253	0	1
308	0	1
409	0	8
410	0	8
412	0	8
413	0	8
415	0	8
416	0	8
420	0	1
422	0	1
425	0	1
426	0	1
427	0	1
428	0	1
433	0	1
437	0	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	0	0.00
Logical	58	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	55	90.16
Total Bits	2882	2796	97.02
Total Bits 0->1	1441	1398	97.02
Total Bits 1->0	1441	1398	97.02

Ports	61	55	90.16
Port Bits	2882	2796	97.02
Port Bits 0->1	1441	1398	97.02
Port Bits 1->0	1441	1398	97.02

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T7,T4	Yes	T2,T4,T5	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T7,T4	Yes	T2,T4,T5	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T2,T7,T4	Yes	T2,T4,T5	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T7,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T7,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rom_tl_i.a_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
rom_tl_o.a_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T2,T5,T11	Yes	T2,T5,T11	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T4,T5,T13	Yes	T2,T4,T5	OUTPUT
regs_tl_o.d_user.data_intg[1:0]	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[2]	Yes	Yes	*T4,*T5,*T13	Yes	T4,T5,T13	OUTPUT
regs_tl_o.d_user.data_intg[3]	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[4]	Yes	Yes	*T4,*T5,*T13	Yes	T4,T5,T13	OUTPUT
regs_tl_o.d_user.data_intg[5]	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6]	Yes	Yes	T4,T5,T13	Yes	T4,T5,T13	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T14	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T8,T9,T10	OUTPUT
keymgr_data_o.valid	Yes	Yes	T8,T9,T10	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T8,T9,T10	Yes	T3,T14,T7	OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T8,T9,T15	Yes	T8,T9,T10	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T8,T9,T10	Yes	T8,T10,T16	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
TERNARY	207	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered