Unified Coverage Report :: Module :: prim_subst_perm

Module : prim_subst_perm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_sp_addr	0.00	0.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_sp_addr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						gen_rom_scramble_enabled.u_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_subst_perm

	Line No.	Total	Covered	Percent
TOTAL		22	0	0.00
CONT_ASSIGN	35	1	0	0.00
ALWAYS	64	10	0	0.00
ALWAYS	64	10	0	0.00
CONT_ASSIGN	90	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	0	1
64	0	1
68	0	1
69	0	1
72	0	1
73	0	1
78	0	1
79	0	1
80	0	1
81	0	1
83	0	1
64	0	1
68	0	1
69	0	1
72	0	1
73	0	1
78	0	1
79	0	1
80	0	1
81	0	1
83	0	1
90	0	1