9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.317m | 46.348ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 36.260s | 3.480ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 33.750s | 17.134ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 25.480s | 43.755ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 31.730s | 16.529ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 33.300s | 4.736ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 33.750s | 17.134ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 31.730s | 16.529ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 30.650s | 7.999ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 27.560s | 6.644ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 35.270s | 17.062ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.216m | 17.984ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.181m | 8.931ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 32.510s | 4.121ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 36.190s | 42.909ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 36.190s | 42.909ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 36.260s | 3.480ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.750s | 17.134ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 31.730s | 16.529ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 35.030s | 3.771ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 36.260s | 3.480ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 33.750s | 17.134ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 31.730s | 16.529ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 35.030s | 3.771ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.087m | 90.507ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.126m | 4.814ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.971m | 4.397ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.126m | 4.814ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.126m | 4.814ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.126m | 4.814ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.317m | 46.348ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.317m | 46.348ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.317m | 46.348ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.971m | 4.397ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.181m | 8.931ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 22.037m | 128.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.087m | 90.507ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.126m | 4.814ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.360h | 23.902ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 459 | 500 | 91.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
0.rom_ctrl_stress_all_with_rand_reset.51889471042079953227351710351763266394154846183454342501130347467167150801522
Line 298, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19160828078 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19160828078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_ctrl_stress_all_with_rand_reset.4312806466909366181014913354758859120759024542209121542112584661590227569817
Line 450, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52579353088 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 52579353088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
4.rom_ctrl_stress_all_with_rand_reset.4440937037336889049112330672565933727313466189274263055855389212988042454374
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ba324bfd-f029-45be-99a1-dc0089df78ae
11.rom_ctrl_stress_all_with_rand_reset.57351778843894515233397956604715126876603435840777667791361261908407276277773
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8c898fd5-055f-4b6e-bb46-19acc97f58e2
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
23.rom_ctrl_stress_all_with_rand_reset.25759452524522933374513866751555030252678065235885995099188029660516876138901
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10005043669 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x449e574f
UVM_INFO @ 10005043669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rom_ctrl_stress_all_with_rand_reset.13466278457654410703127208114533357104932389892885700072366780482387406845659
Line 264, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10727155009 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x56256c20
UVM_INFO @ 10727155009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
31.rom_ctrl_corrupt_sig_fatal_chk.33711327601317721231743403998900383554569576932998791444862622922382860946784
Line 294, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
41.rom_ctrl_smoke.13378994388568969941651070322170193785975021071604926831958514177248196378772
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/41.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40013308304 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xef598ed6
UVM_INFO @ 40013308304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rom_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log
Job ID: smart:20f541b5-a89a-4a9a-b830-e7f15c86b7b7