1c75f24e99| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.361m | 17.384ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 34.730s | 6.624ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 32.240s | 4.099ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 31.540s | 15.733ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 32.330s | 16.476ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 34.860s | 4.390ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 32.240s | 4.099ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 32.330s | 16.476ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 28.520s | 3.737ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 28.570s | 5.132ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 34.870s | 25.612ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.465m | 48.319ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.151m | 8.446ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.040s | 17.183ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 37.270s | 4.293ms | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 37.270s | 4.293ms | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 34.730s | 6.624ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.240s | 4.099ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.330s | 16.476ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.130s | 4.035ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 34.730s | 6.624ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 32.240s | 4.099ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 32.330s | 16.476ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.130s | 4.035ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 237 | 240 | 98.75 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.326m | 34.735ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.034m | 3.960ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.915m | 19.290ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.034m | 3.960ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.034m | 3.960ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.034m | 3.960ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.361m | 17.384ms | 47 | 50 | 94.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.361m | 17.384ms | 47 | 50 | 94.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.361m | 17.384ms | 47 | 50 | 94.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.915m | 19.290ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 1.151m | 8.446ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 14.438m | 83.470ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.326m | 34.735ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.034m | 3.960ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.111h | 66.850ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 455 | 500 | 91.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 3 | 50.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
0.rom_ctrl_stress_all_with_rand_reset.12788360307080155869474335358230678275259643843123171522241671978956079655710
Line 385, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24918061041 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24918061041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.62725983499580994427542462796379709316406562408678319365388248219550637828199
Line 315, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9118542801 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9118542801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
9.rom_ctrl_stress_all_with_rand_reset.29810400683333311428595444545880423195218566716532098467591017273050073451032
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10005016096 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x145adc57
UVM_INFO @ 10005016096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rom_ctrl_stress_all_with_rand_reset.111527075482634304525504827775376137171849551701796013680630250207208902301611
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12241445590 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x70b90900
UVM_INFO @ 12241445590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 4 failures:
6.rom_ctrl_smoke.58758830124043595711322830372659476887921096316699745972867342309071725942408
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40012974810 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7e930f6d
UVM_INFO @ 40012974810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rom_ctrl_smoke.57798269328745720986810470356117629944531688244376744620515392599189532936509
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 40010092662 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x68ded0c6
UVM_INFO @ 40010092662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
38.rom_ctrl_stress_all.50866231693089064518229806575900410556014251849627170592633365280068235623985
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/38.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 40274215178 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4790aa64
UVM_INFO @ 40274215178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
15.rom_ctrl_stress_all_with_rand_reset.63078924032882835784591770574747229806157673745017345112668319564777228798425
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:941aa3da-527b-454b-bc49-d5aaf91bf83a
24.rom_ctrl_stress_all_with_rand_reset.77824268046583940544158925119900846387747901409327927784997199265409586558886
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:890e92a9-a36c-4a34-b705-9daf4e90ea27
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
Test rom_ctrl_tl_errors has 1 failures.
9.rom_ctrl_tl_errors.98623106867092164301720099695680537109371408282343259703696389122178806507579
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_tl_errors/latest/run.log
UVM_ERROR @ 2747693998 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 2747693998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_kmac_err_chk has 1 failures.
39.rom_ctrl_kmac_err_chk.77969496343498235595020693577502625118508526225656373573949416711437287188918
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/39.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 5498561806 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 5498561806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
23.rom_ctrl_corrupt_sig_fatal_chk.5248375496704824613971253531591270864686739706331528383965144197332398406085
Line 281, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rom_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log
Job ID: smart:ca14b901-22b9-4089-a6f5-a1f875e1cda5