ROM_CTRL/32KB Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.680s	15.734ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.860s	7.923ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.430s	4.531ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.150s	7.875ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.040s	4.378ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.580s	7.927ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.430s	4.531ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.040s	4.378ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.180s	1.969ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.780s	1.941ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.470s	7.894ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.042m	96.227ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.810s	4.195ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.380s	2.065ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.280s	6.447ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.280s	6.447ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.860s	7.923ms	5	5	100.00
		rom_ctrl_csr_rw	16.430s	4.531ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.040s	4.378ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.330s	28.775ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.860s	7.923ms	5	5	100.00
		rom_ctrl_csr_rw	16.430s	4.531ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.040s	4.378ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.330s	28.775ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.535m	45.436ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.776m	1.307ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.304m	660.892us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.776m	1.307ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.776m	1.307ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.776m	1.307ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.680s	15.734ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.680s	15.734ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.680s	15.734ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.304m	660.892us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.810s	4.195ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.257m	373.130ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.535m	45.436ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.776m	1.307ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.106h	363.982ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	96.97	93.15	97.88	100.00	98.69	98.03	98.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.29066767032822714845974761198922969141195920755800319342097036343678870889479
      Line 312, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8216965894 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8216965894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.87825297798606842596294310209183992418487781577238223281093057661310425335869
      Line 366, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53287473181 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 53287473181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 10 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.7339569408082891762024079491862040130023142435381411480559372657470135966461
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:bf1a3377-0a28-4c48-b1b7-905b0b34577d
      

    • 9.rom_ctrl_stress_all_with_rand_reset.24854358451088644172350899573411053761948301187616492218722149172084131941738
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:edeef468-ad42-44d7-b9b2-3ce93efe9a46
      

    • ... and 8 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 7.rom_ctrl_stress_all.18816310505402352750825596701742540628212502894476035449430599440333521416057
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 112402920183 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 112402920183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.rom_ctrl_stress_all_with_rand_reset.2537850765263651082669784836673933073090009489284956760033949800358785797764
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11407976751 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd5dfb45c
        UVM_INFO @ 11407976751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.29_08.06.08
• 2024.04.26_07.56.37
• 2024.04.24_08.07.19
• 2024.04.22_07.31.13