ROM_CTRL/64KB Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.244m	15.769ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	35.560s	3.720ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.400s	4.509ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.010s	24.010ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.550s	6.654ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.280s	7.192ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.400s	4.509ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.550s	6.654ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.390s	3.661ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	30.900s	73.728ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.000s	15.795ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.962m	91.286ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.211m	170.295ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	32.160s	16.641ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	38.380s	17.477ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	38.380s	17.477ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	35.560s	3.720ms	5	5	100.00
		rom_ctrl_csr_rw	31.400s	4.509ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.550s	6.654ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.910s	32.217ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	35.560s	3.720ms	5	5	100.00
		rom_ctrl_csr_rw	31.400s	4.509ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.550s	6.654ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	35.910s	32.217ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.423m	111.769ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.913m	6.488ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.853m	4.359ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.913m	6.488ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.913m	6.488ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.913m	6.488ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.244m	15.769ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.244m	15.769ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.244m	15.769ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.853m	4.359ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.211m	170.295ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.788m	372.249ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.423m	111.769ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.913m	6.488ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.920h	47.180ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.97	93.15	97.88	100.00	98.69	98.03	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.66073835504645694667413983675286484870808745089527695522327710843680405796135
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6857853173 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6857853173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_ctrl_stress_all_with_rand_reset.78990596065566782397769957438082537739226311193834522351603181573683769315849
      Line 284, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6197119235 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6197119235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 8 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.29393054435241214131352986140538907031436152873934129448623696723158440084957
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:546517f9-c487-421b-b0c6-1e41fcef4a27
      

    • 7.rom_ctrl_stress_all_with_rand_reset.96822523387616118197728956578448097544518240686443000272980710308190988121279
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:753ef44e-c36c-41aa-ab3f-241aa4e278d2
      

    • ... and 6 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 5.rom_ctrl_stress_all_with_rand_reset.41618852812140491566512952738301983116184854796009796972384446318780299233608
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10008228627 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe46cf25e
        UVM_INFO @ 10008228627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.rom_ctrl_stress_all_with_rand_reset.78640573384508489870450953550488035524863047663605180783297152221875991532293
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10003305554 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2a4e9a6b
        UVM_INFO @ 10003305554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

Past Results

• Latest
• 2024.04.29_08.06.54
• 2024.04.26_07.57.31
• 2024.04.24_08.08.04
• 2024.04.22_07.31.34