RSTMGR Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.640s	240.036us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.940s	134.788us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.520s	2.292ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.690s	240.651us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.580s	168.998us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
		rstmgr_csr_aliasing	1.690s	240.651us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.020s	221.235us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.950s	521.253us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.600s	291.080us	50	50	100.00
V2	reset_info	rstmgr_reset	7.350s	2.128ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.350s	2.128ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.350s	2.128ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.350s	2.128ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	47.280s	13.718ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.920s	91.402us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.000s	554.277us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.000s	554.277us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.940s	134.788us	5	5	100.00
		rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
		rstmgr_csr_aliasing	1.690s	240.651us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	256.864us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.940s	134.788us	5	5	100.00
		rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
		rstmgr_csr_aliasing	1.690s	240.651us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	256.864us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	26.140s	17.793ms	5	5	100.00
		rstmgr_tl_intg_err	3.550s	910.833us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	26.140s	17.793ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	26.140s	17.793ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.550s	910.833us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.280s	163.077us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.100s	2.369ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.230s	244.233us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	26.140s	17.793ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.860s	68.912us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test rstmgr has 1 failures.

cov_merge
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/cov_merge/merged.vdb/cov_merge.log

              Inclusivity and Diversity" (Refer to article 000036315 at
                          https://solvnetplus.synopsys.com)
  
  Error-[URG-NLCW] No license key
    URG failed to get a license key. Number of attempts to get a license key
    exceeded the limit (500).
    Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
    file.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:220: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test rstmgr has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/cov_report/cov_report.log