RSTMGR Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.690s	259.444us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.950s	130.705us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.500s	2.298ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.530s	399.201us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.510s	156.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
		rstmgr_csr_aliasing	2.530s	399.201us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.000s	176.660us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	3.020s	551.459us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.550s	287.875us	50	50	100.00
V2	reset_info	rstmgr_reset	7.950s	2.119ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.950s	2.119ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.950s	2.119ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.950s	2.119ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.190s	13.880ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.860s	77.291us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.310s	443.831us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.310s	443.831us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.950s	130.705us	5	5	100.00
		rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
		rstmgr_csr_aliasing	2.530s	399.201us	5	5	100.00
		rstmgr_same_csr_outstanding	1.560s	260.375us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.950s	130.705us	5	5	100.00
		rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
		rstmgr_csr_aliasing	2.530s	399.201us	5	5	100.00
		rstmgr_same_csr_outstanding	1.560s	260.375us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	29.320s	16.524ms	5	5	100.00
		rstmgr_tl_intg_err	3.450s	885.122us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	29.320s	16.524ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	29.320s	16.524ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.450s	885.122us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.220s	142.372us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.760s	2.369ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.210s	244.568us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	29.320s	16.524ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	1.000s	84.198us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.01.18_08.46.22
• 2024.01.15_04.04.02
• 2024.01.11_03.17.46
• 2024.01.08_03.04.33
• 2024.01.04_01.28.56