Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T60,T77
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T61,T62
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13224784	14371	0	0
gen_assertions[0].RstEnOn_A	13224784	1145	0	0
gen_assertions[0].RstNOff_A	13224784	14371	0	0
gen_assertions[0].RstNOn_A	13224784	1145	0	0
gen_assertions[1].RstEnOff_A	52899386	13089	0	0
gen_assertions[1].RstEnOn_A	52899386	1115	0	0
gen_assertions[1].RstNOff_A	52899386	13089	0	0
gen_assertions[1].RstNOn_A	52899386	1115	0	0
gen_assertions[2].RstEnOff_A	26450597	13116	0	0
gen_assertions[2].RstEnOn_A	26450597	1082	0	0
gen_assertions[2].RstNOff_A	26450597	13116	0	0
gen_assertions[2].RstNOn_A	26450597	1082	0	0
gen_assertions[3].RstEnOff_A	26450558	13191	0	0
gen_assertions[3].RstEnOn_A	26450558	1149	0	0
gen_assertions[3].RstNOff_A	26450558	13191	0	0
gen_assertions[3].RstNOn_A	26450558	1149	0	0
gen_assertions[4].RstEnOff_A	1670472	22393	0	0
gen_assertions[4].RstEnOn_A	1670472	1176	0	0
gen_assertions[4].RstNOff_A	1670472	22393	0	0
gen_assertions[4].RstNOn_A	1670472	1176	0	0
gen_assertions[5].RstEnOff_A	13224784	14629	0	0
gen_assertions[5].RstEnOn_A	13224784	1256	0	0
gen_assertions[5].RstNOff_A	13224784	14629	0	0
gen_assertions[5].RstNOn_A	13224784	1256	0	0
gen_assertions[6].RstEnOff_A	13224784	14676	0	0
gen_assertions[6].RstEnOn_A	13224784	1303	0	0
gen_assertions[6].RstNOff_A	13224784	14676	0	0
gen_assertions[6].RstNOn_A	13224784	1303	0	0
gen_assertions[7].RstEnOff_A	13224784	14716	0	0
gen_assertions[7].RstEnOn_A	13224784	1333	0	0
gen_assertions[7].RstNOff_A	13224784	14716	0	0
gen_assertions[7].RstNOn_A	13224784	1333	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14371	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1145	0	0
T12	2937	6	0	0
T13	5293	0	0	0
T14	3109	0	0	0
T22	44247	0	0	0
T23	29188	0	0	0
T24	3113	3	0	0
T25	29127	0	0	0
T55	1936	0	0	0
T60	7210	1	0	0
T61	0	7	0	0
T62	0	2	0	0
T73	0	14	0	0
T74	0	7	0	0
T77	2192	1	0	0
T78	0	2	0	0
T79	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14371	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1145	0	0
T12	2937	6	0	0
T13	5293	0	0	0
T14	3109	0	0	0
T22	44247	0	0	0
T23	29188	0	0	0
T24	3113	3	0	0
T25	29127	0	0	0
T55	1936	0	0	0
T60	7210	1	0	0
T61	0	7	0	0
T62	0	2	0	0
T73	0	14	0	0
T74	0	7	0	0
T77	2192	1	0	0
T78	0	2	0	0
T79	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	13089	0	0
T1	23765	5	0	0
T2	148239	41	0	0
T3	12916	6	0	0
T4	7029	0	0	0
T5	11639	0	0	0
T6	6825	0	0	0
T7	161435	31	0	0
T8	181463	72	0	0
T9	14629	0	0	0
T10	6451	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	1115	0	0
T1	23765	1	0	0
T2	148239	0	0	0
T3	12916	0	0	0
T4	7029	0	0	0
T5	11639	0	0	0
T6	6825	0	0	0
T7	161435	0	0	0
T8	181463	0	0	0
T9	14629	0	0	0
T10	6451	0	0	0
T60	0	5	0	0
T61	0	7	0	0
T62	0	3	0	0
T73	0	14	0	0
T74	0	4	0	0
T77	0	3	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	13089	0	0
T1	23765	5	0	0
T2	148239	41	0	0
T3	12916	6	0	0
T4	7029	0	0	0
T5	11639	0	0	0
T6	6825	0	0	0
T7	161435	31	0	0
T8	181463	72	0	0
T9	14629	0	0	0
T10	6451	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	1115	0	0
T1	23765	1	0	0
T2	148239	0	0	0
T3	12916	0	0	0
T4	7029	0	0	0
T5	11639	0	0	0
T6	6825	0	0	0
T7	161435	0	0	0
T8	181463	0	0	0
T9	14629	0	0	0
T10	6451	0	0	0
T60	0	5	0	0
T61	0	7	0	0
T62	0	3	0	0
T73	0	14	0	0
T74	0	4	0	0
T77	0	3	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	13116	0	0
T1	11886	4	0	0
T2	74110	41	0	0
T3	6458	6	0	0
T4	3515	0	0	0
T5	5818	0	0	0
T6	3411	0	0	0
T7	80726	31	0	0
T8	90745	72	0	0
T9	7313	0	0	0
T10	3225	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	1082	0	0
T14	6217	0	0	0
T25	58243	0	0	0
T56	6873	0	0	0
T57	423949	0	0	0
T60	14421	4	0	0
T61	7379	9	0	0
T62	0	3	0	0
T71	38573	0	0	0
T72	94252	0	0	0
T73	0	9	0	0
T74	0	5	0	0
T75	11670	0	0	0
T78	3723	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	4	0	0
T82	0	23	0	0
T83	0	16	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	13116	0	0
T1	11886	4	0	0
T2	74110	41	0	0
T3	6458	6	0	0
T4	3515	0	0	0
T5	5818	0	0	0
T6	3411	0	0	0
T7	80726	31	0	0
T8	90745	72	0	0
T9	7313	0	0	0
T10	3225	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	1082	0	0
T14	6217	0	0	0
T25	58243	0	0	0
T56	6873	0	0	0
T57	423949	0	0	0
T60	14421	4	0	0
T61	7379	9	0	0
T62	0	3	0	0
T71	38573	0	0	0
T72	94252	0	0	0
T73	0	9	0	0
T74	0	5	0	0
T75	11670	0	0	0
T78	3723	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	4	0	0
T82	0	23	0	0
T83	0	16	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	13191	0	0
T1	11885	4	0	0
T2	74120	41	0	0
T3	6458	6	0	0
T4	3515	0	0	0
T5	5818	0	0	0
T6	3412	0	0	0
T7	80729	31	0	0
T8	90748	72	0	0
T9	7314	0	0	0
T10	3225	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	1149	0	0
T14	6217	0	0	0
T25	58225	0	0	0
T56	6873	0	0	0
T57	423947	0	0	0
T60	14422	6	0	0
T61	7379	8	0	0
T62	0	5	0	0
T71	38579	0	0	0
T72	94253	0	0	0
T73	0	14	0	0
T74	0	5	0	0
T75	11671	0	0	0
T78	3723	0	0	0
T80	0	3	0	0
T81	0	4	0	0
T82	0	26	0	0
T83	0	19	0	0
T84	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	13191	0	0
T1	11885	4	0	0
T2	74120	41	0	0
T3	6458	6	0	0
T4	3515	0	0	0
T5	5818	0	0	0
T6	3412	0	0	0
T7	80729	31	0	0
T8	90748	72	0	0
T9	7314	0	0	0
T10	3225	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T22	0	32	0	0
T23	0	66	0	0
T24	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	1149	0	0
T14	6217	0	0	0
T25	58225	0	0	0
T56	6873	0	0	0
T57	423947	0	0	0
T60	14422	6	0	0
T61	7379	8	0	0
T62	0	5	0	0
T71	38579	0	0	0
T72	94253	0	0	0
T73	0	14	0	0
T74	0	5	0	0
T75	11671	0	0	0
T78	3723	0	0	0
T80	0	3	0	0
T81	0	4	0	0
T82	0	26	0	0
T83	0	19	0	0
T84	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	22393	0	0
T1	742	6	0	0
T2	4731	61	0	0
T3	402	9	0	0
T4	217	1	0	0
T5	363	2	0	0
T6	213	1	0	0
T7	5098	52	0	0
T8	5686	92	0	0
T9	456	2	0	0
T10	200	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	1176	0	0
T14	388	0	0	0
T25	3654	0	0	0
T56	429	0	0	0
T57	26617	0	0	0
T60	899	8	0	0
T61	459	9	0	0
T62	0	6	0	0
T71	2453	0	0	0
T72	5947	0	0	0
T73	0	11	0	0
T74	0	7	0	0
T75	731	0	0	0
T78	232	0	0	0
T80	0	4	0	0
T81	0	5	0	0
T82	0	25	0	0
T84	0	1	0	0
T85	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	22393	0	0
T1	742	6	0	0
T2	4731	61	0	0
T3	402	9	0	0
T4	217	1	0	0
T5	363	2	0	0
T6	213	1	0	0
T7	5098	52	0	0
T8	5686	92	0	0
T9	456	2	0	0
T10	200	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	1176	0	0
T14	388	0	0	0
T25	3654	0	0	0
T56	429	0	0	0
T57	26617	0	0	0
T60	899	8	0	0
T61	459	9	0	0
T62	0	6	0	0
T71	2453	0	0	0
T72	5947	0	0	0
T73	0	11	0	0
T74	0	7	0	0
T75	731	0	0	0
T78	232	0	0	0
T80	0	4	0	0
T81	0	5	0	0
T82	0	25	0	0
T84	0	1	0	0
T85	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14629	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1256	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	8	0	0
T61	3689	12	0	0
T62	0	7	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	13	0	0
T74	0	7	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T80	0	2	0	0
T81	0	7	0	0
T82	0	27	0	0
T83	0	19	0	0
T84	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14629	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1256	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	8	0	0
T61	3689	12	0	0
T62	0	7	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	13	0	0
T74	0	7	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T80	0	2	0	0
T81	0	7	0	0
T82	0	27	0	0
T83	0	19	0	0
T84	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14676	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1303	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	9	0	0
T61	3689	12	0	0
T62	0	7	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	13	0	0
T74	0	7	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	7	0	0
T82	0	22	0	0
T84	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14676	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1303	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	9	0	0
T61	3689	12	0	0
T62	0	7	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	13	0	0
T74	0	7	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	7	0	0
T82	0	22	0	0
T84	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14716	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1333	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	11	0	0
T61	3689	12	0	0
T62	0	8	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	15	0	0
T74	0	5	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	8	0	0
T84	0	1	0	0
T85	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	14716	0	0
T1	5942	4	0	0
T2	37060	43	0	0
T3	3228	8	0	0
T4	1757	0	0	0
T5	2908	0	0	0
T6	1706	0	0	0
T7	40365	32	0	0
T8	45374	75	0	0
T9	3656	0	0	0
T10	1611	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T22	0	37	0	0
T23	0	75	0	0
T24	0	8	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	1333	0	0
T14	3109	0	0	0
T25	29127	0	0	0
T56	3435	0	0	0
T57	211932	0	0	0
T60	7210	11	0	0
T61	3689	12	0	0
T62	0	8	0	0
T71	19293	0	0	0
T72	47119	0	0	0
T73	0	15	0	0
T74	0	5	0	0
T75	5835	0	0	0
T78	1861	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	8	0	0
T84	0	1	0	0
T85	0	1	0	0