Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rstmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.01 100.00 98.21 97.84 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_0.1/rtl/autogen/rstmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 99.55 100.00 98.21 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.40 99.31 99.88 99.83 99.46


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00 100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon 96.65 95.83 97.44 93.33 100.00
gen_rst_por_aon[0].u_por_scanmode_sync 100.00 100.00 100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux 100.00 100.00 100.00 100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync 100.00 100.00 100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00 100.00
gen_rst_por_aon[1].u_por_scanmode_sync 100.00 100.00 100.00
pwrmgr_rstmgr_sva_if 100.00 100.00 100.00 100.00
rstmgr_attrs_sva_if 100.00 100.00
rstmgr_cascading_sva_if 100.00 100.00 100.00 100.00
rstmgr_csr_assert 100.00 100.00
rstmgr_rst_en_track_sva_if 92.86 92.86
rstmgr_sw_rst_sva_if 100.00 100.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_alert_info 100.00 100.00 100.00 100.00
u_cpu_info 100.00 100.00 100.00 100.00
u_ctrl_scanmode_sync 100.00 100.00 100.00
u_d0_i2c0 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_i2c1 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_i2c2 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_lc 100.00 100.00 100.00 100.00 100.00 100.00
u_d0_lc_io 100.00 100.00 100.00 100.00 100.00 100.00
u_d0_lc_io_div2 100.00 100.00 100.00 100.00 100.00 100.00
u_d0_lc_io_div4 100.00 100.00 100.00 100.00 100.00
u_d0_lc_io_div4_shadowed 100.00 100.00 100.00 100.00 100.00
u_d0_lc_shadowed 96.47 100.00 100.00 82.35 100.00 100.00
u_d0_lc_usb 100.00 100.00 100.00 100.00 100.00 100.00
u_d0_spi_device 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_spi_host0 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_spi_host1 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_sys 100.00 100.00 100.00 100.00 100.00 100.00
u_d0_usb 99.29 100.00 96.43 100.00 100.00 100.00
u_d0_usb_aon 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc_aon 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc_io 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc_io_div2 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc_io_div4 100.00 100.00 100.00 100.00 100.00
u_daon_lc_io_div4_shadowed 100.00 100.00 100.00 100.00 100.00
u_daon_lc_shadowed 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_lc_usb 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_por 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_por_io 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_por_io_div2 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_por_io_div4 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_por_usb 100.00 100.00 100.00 100.00 100.00 100.00
u_daon_sys_io_div4 100.00 100.00 100.00 100.00 100.00 100.00
u_lc_src 100.00 100.00 100.00 100.00 100.00
u_por_clk_buf 100.00 100.00
u_por_rst_buf 100.00 100.00
u_reg 99.65 98.40 99.85 100.00 100.00 100.00
u_sys_src 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : rstmgr
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN118811100.00
CONT_ASSIGN119311100.00
CONT_ASSIGN119511100.00
CONT_ASSIGN119911100.00
CONT_ASSIGN120311100.00
CONT_ASSIGN120811100.00
CONT_ASSIGN121211100.00
CONT_ASSIGN121411100.00
CONT_ASSIGN121811100.00
CONT_ASSIGN122011100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN126011100.00
CONT_ASSIGN126211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_0.1/rtl/autogen/rstmgr.sv' or '../src/lowrisc_systems_rstmgr_0.1/rtl/autogen/rstmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
148 1 1
202 1 1
204 1 1
207 1 1
214 1 1
217 1 1
219 1 1
285 1 1
286 1 1
1188 1 1
1193 1 1
1195 1 1
1199 1 1
1203 1 1
1208 1 1
1212 1 1
1214 1 1
1218 1 1
1220 1 1
1227 1 1
1231 1 1
1260 1 1
1262 1 1


Cond Coverage for Module : rstmgr
TotalCoveredPercent
Conditions565598.21
Logical565598.21
Non-Logical00
Event00

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1])
             -------------------1-------------------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T7
11CoveredT1,T2,T3

 LINE       204
 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)))
             ---------1---------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T23,T25
10CoveredT8,T23,T25

 LINE       207
 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs)))
             ------1------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T57,T68
10CoveredT21,T57,T68

 LINE       214
 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q)))
             ---------------1--------------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T57,T68
10CoveredT21,T57,T68

 LINE       219
 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT4,T6,T10
10CoveredT1,T2,T3
11CoveredT4,T6,T10

 LINE       219
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT4,T6,T10
10CoveredT1,T2,T3
11CoveredT4,T6,T10

 LINE       1188
 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req)))
             ----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       1193
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1193
 SUB-EXPRESSION (pwr_i.reset_cause == HwReq)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1195
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry))
             -------1------   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T7

 LINE       1195
 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       1227
 EXPRESSION (rst_hw_req | rst_low_power)
             -----1----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T7
10CoveredT1,T2,T3

 LINE       1235
 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q)
             ------1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1247
 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q)
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Toggle Coverage for Module : rstmgr
TotalCoveredPercent
Totals 84 68 80.95
Total Bits 1482 1450 97.84
Total Bits 0->1 741 725 97.84
Total Bits 1->0 741 725 97.84

Ports 84 68 80.95
Port Bits 1482 1450 97.84
Port Bits 0->1 741 725 97.84
Port Bits 1->0 741 725 97.84

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_div4_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_div2_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_por_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_por_ni Yes Yes T1,T2,T5 Yes T1,T2,T3 INPUT
por_n_i[1:0] Yes Yes T2,T5,T7 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T7,T21,T12 Yes T7,T21,T12 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T63,T64,T65 Yes T67,T63,T64 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T6,T10 Yes T4,T6,T10 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T4,T6,T10 Yes T4,T6,T10 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T6,T10 Yes T4,T6,T10 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T4,T6,T8 Yes T4,T6,T8 OUTPUT
pwr_i.reset_cause[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_i.rstreqs[4:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
pwr_i.rst_sys_req[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_i.rst_lc_req[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_o.rst_sys_src_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_o.rst_lc_src_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sw_rst_req_o[3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
alert_dump_i.class_esc_cnt[0][4:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][10:8] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][12] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][13] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][20:14] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][22:21] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][23] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][24] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][25] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][26] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][30:27] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][31] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][8:1] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][9] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][20:10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][21] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][27:22] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][29:28] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][31:30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][6:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][28:8] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][29] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][31:30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][2:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][3] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][13:4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][14] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][21:15] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][22] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][25:23] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][26] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][29:27] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][31] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][9:5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][15:11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][8:7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][9] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][15:12] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][4:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][9:6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][14:11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][15] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][1] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][2] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][15:3] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.loc_alert_cause[6:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.alert_cause[64:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.exception_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.exception_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.last_data_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.next_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.current_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_exception_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_exception_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_valid Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
scan_rst_ni Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
scanmode_i[3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
resets_o.rst_i2c2_n[0] No No No OUTPUT
resets_o.rst_i2c2_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_i2c1_n[0] No No No OUTPUT
resets_o.rst_i2c1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_i2c0_n[0] No No No OUTPUT
resets_o.rst_i2c0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_usb_aon_n[0] No No No OUTPUT
resets_o.rst_usb_aon_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_usb_n[0] No No No OUTPUT
resets_o.rst_usb_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_host1_n[0] No No No OUTPUT
resets_o.rst_spi_host1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_host0_n[0] No No No OUTPUT
resets_o.rst_spi_host0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_device_n[0] No No No OUTPUT
resets_o.rst_spi_device_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_sys_io_div4_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_sys_io_div4_n[1] No No No OUTPUT
resets_o.rst_sys_n[0] No No No OUTPUT
resets_o.rst_sys_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_usb_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div4_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div2_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_aon_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_aon_n[1] No No No OUTPUT
resets_o.rst_lc_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_usb_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_usb_n[1] No No No OUTPUT
resets_o.rst_por_io_div4_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_div4_n[1] No No No OUTPUT
resets_o.rst_por_io_div2_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_div2_n[1] No No No OUTPUT
resets_o.rst_por_io_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_n[1] No No No OUTPUT
resets_o.rst_por_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_n[1] No No No OUTPUT
resets_o.rst_por_aon_n[1:0] Yes Yes T1,T2,T5 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : rstmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 34 34 100.00 34 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 34 34 100.00 34 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 11680055 6711352 0 0
FpvSecCmRegWeOnehotCheck_A 11680055 80 0 0
ParameterMatch_A 503 503 0 0
PwrKnownO_A 11680055 6711352 0 0
ResetsKnownO_A 11680055 6711352 0 0
RstEnKnownO_A 11680055 6711352 0 0
TlAReadyKnownO_A 11680055 6711352 0 0
TlDValidKnownO_A 11680055 6711352 0 0
gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 11680055 80 0 0
gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 11680055 80 0 0
gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 11680055 80 0 0
gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 11680055 80 0 0
gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 11680055 80 0 0
gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 11680055 80 0 0
gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 11680055 80 0 0
gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 11680055 80 0 0
gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 11680055 80 0 0
gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 11680055 80 0 0
gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 11680055 80 0 0
gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 11680055 80 0 0
gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 11680055 80 0 0
gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 11680055 80 0 0
gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 11680055 80 0 0
gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 11680055 80 0 0
gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 11680055 80 0 0
gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 11680055 80 0 0
gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 11680055 80 0 0
gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 11680055 80 0 0
gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 11680055 80 0 0
gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 11680055 80 0 0
gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 11680055 80 0 0
gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 11680055 80 0 0
gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 11680055 80 0 0
gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 11680055 80 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

ParameterMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PwrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

ResetsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

RstEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN118811100.00
CONT_ASSIGN119311100.00
CONT_ASSIGN119511100.00
CONT_ASSIGN119911100.00
CONT_ASSIGN120311100.00
CONT_ASSIGN120811100.00
CONT_ASSIGN121211100.00
CONT_ASSIGN121411100.00
CONT_ASSIGN121811100.00
CONT_ASSIGN122011100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN126011100.00
CONT_ASSIGN126211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_0.1/rtl/autogen/rstmgr.sv' or '../src/lowrisc_systems_rstmgr_0.1/rtl/autogen/rstmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
148 1 1
202 1 1
204 1 1
207 1 1
214 1 1
217 1 1
219 1 1
285 1 1
286 1 1
1188 1 1
1193 1 1
1195 1 1
1199 1 1
1203 1 1
1208 1 1
1212 1 1
1214 1 1
1218 1 1
1220 1 1
1227 1 1
1231 1 1
1260 1 1
1262 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions565598.21
Logical565598.21
Non-Logical00
Event00

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       37
 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1])
             -------------------1-------------------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T7
11CoveredT1,T2,T3

 LINE       204
 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)))
             ---------1---------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T23,T25
10CoveredT8,T23,T25

 LINE       207
 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs)))
             ------1------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T57,T68
10CoveredT21,T57,T68

 LINE       214
 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q)))
             ---------------1--------------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T57,T68
10CoveredT21,T57,T68

 LINE       219
 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe)
                 ------------------1------------------   -------------------2------------------
-1--2-StatusTests
01CoveredT4,T6,T10
10CoveredT1,T2,T3
11CoveredT4,T6,T10

 LINE       219
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT4,T6,T10
10CoveredT1,T2,T3
11CoveredT4,T6,T10

 LINE       1188
 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req)))
             ----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       1193
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1193
 SUB-EXPRESSION (pwr_i.reset_cause == HwReq)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1195
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry))
             -------1------   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T7

 LINE       1195
 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       1227
 EXPRESSION (rst_hw_req | rst_low_power)
             -----1----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T7
10CoveredT1,T2,T3

 LINE       1235
 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q)
             ------1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1247
 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q)
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 84 84 100.00
Total Bits 1450 1450 100.00
Total Bits 0->1 725 725 100.00
Total Bits 1->0 725 725 100.00

Ports 84 84 100.00
Port Bits 1450 1450 100.00
Port Bits 0->1 725 725 100.00
Port Bits 1->0 725 725 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_div4_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_io_div2_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_por_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_por_ni Yes Yes T1,T2,T5 Yes T1,T2,T3 INPUT
por_n_i[1:0] Yes Yes T2,T5,T7 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T7,T21,T12 Yes T7,T21,T12 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T63,T64,T65 Yes T67,T63,T64 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T6,T10 Yes T4,T6,T10 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T4,T6,T10 Yes T4,T6,T10 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T6,T10 Yes T4,T6,T10 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T4,T6,T8 Yes T4,T6,T8 OUTPUT
pwr_i.reset_cause[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_i.rstreqs[4:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
pwr_i.rst_sys_req[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_i.rst_lc_req[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
pwr_o.rst_sys_src_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_o.rst_lc_src_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sw_rst_req_o[3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
alert_dump_i.class_esc_cnt[0][4:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][10:8] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][12] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][13] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][20:14] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][22:21] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][23] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][24] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][25] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][26] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][30:27] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[0][31] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][8:1] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][9] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][20:10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][21] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][27:22] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][29:28] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[1][31:30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][6:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][28:8] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][29] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[2][31:30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][2:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][3] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][13:4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][14] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][21:15] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][22] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][25:23] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][26] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][29:27] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][30] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_esc_cnt[3][31] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][9:5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[0][15:11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][4] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][8:7] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][9] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[1][15:12] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][4:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][9:6] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][10] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][14:11] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[2][15] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][1] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][2] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.class_accum_cnt[3][15:3] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.loc_alert_cause[6:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
alert_dump_i.alert_cause[64:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.exception_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.exception_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.last_data_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.next_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.current.current_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_exception_addr[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_exception_pc[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
cpu_dump_i.prev_valid Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
scan_rst_ni Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
scanmode_i[3:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
resets_o.rst_i2c2_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_i2c2_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_i2c1_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_i2c1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_i2c0_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_i2c0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_usb_aon_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_usb_aon_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_usb_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_usb_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_host1_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_spi_host1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_host0_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_spi_host0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_spi_device_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_spi_device_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_sys_io_div4_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_sys_io_div4_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_sys_n[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_sys_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_usb_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div4_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_div2_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_io_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_aon_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_aon_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_lc_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_lc_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_usb_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_usb_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_por_io_div4_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_div4_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_por_io_div2_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_div2_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_por_io_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_io_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_por_n[0] Yes Yes *T1,*T2,*T5 Yes T1,T2,T3 OUTPUT
resets_o.rst_por_n[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
resets_o.rst_por_aon_n[1:0] Yes Yes T1,T2,T5 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 34 34 100.00 34 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 34 34 100.00 34 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 11680055 6711352 0 0
FpvSecCmRegWeOnehotCheck_A 11680055 80 0 0
ParameterMatch_A 503 503 0 0
PwrKnownO_A 11680055 6711352 0 0
ResetsKnownO_A 11680055 6711352 0 0
RstEnKnownO_A 11680055 6711352 0 0
TlAReadyKnownO_A 11680055 6711352 0 0
TlDValidKnownO_A 11680055 6711352 0 0
gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 11680055 80 0 0
gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 11680055 80 0 0
gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 11680055 80 0 0
gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 11680055 80 0 0
gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 11680055 80 0 0
gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 11680055 80 0 0
gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 11680055 80 0 0
gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 11680055 80 0 0
gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 11680055 80 0 0
gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 11680055 80 0 0
gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 11680055 80 0 0
gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 11680055 80 0 0
gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 11680055 80 0 0
gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 11680055 80 0 0
gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 11680055 80 0 0
gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 11680055 80 0 0
gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 11680055 80 0 0
gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 11680055 80 0 0
gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 11680055 80 0 0
gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 11680055 80 0 0
gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 11680055 80 0 0
gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 11680055 80 0 0
gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 11680055 80 0 0
gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 11680055 80 0 0
gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 11680055 80 0 0
gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 11680055 80 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

ParameterMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PwrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

ResetsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

RstEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6711352 0 0
T1 5749 4737 0 0
T2 31342 23009 0 0
T3 2638 1912 0 0
T4 1690 1084 0 0
T5 2842 600 0 0
T6 1615 1044 0 0
T7 35484 25817 0 0
T8 42227 24793 0 0
T9 3518 859 0 0
T10 1569 943 0 0

gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 80 0 0
T11 4044 0 0 0
T12 2243 0 0 0
T13 5251 0 0 0
T14 3066 0 0 0
T21 378832 20 0 0
T22 38996 0 0 0
T23 26203 0 0 0
T24 2544 0 0 0
T25 26270 0 0 0
T57 0 10 0 0
T60 7144 0 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%