Line Coverage for Module :
rstmgr_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 178 | 178 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 223 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
CONT_ASSIGN | 909 | 1 | 1 | 100.00 |
CONT_ASSIGN | 941 | 1 | 1 | 100.00 |
CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1005 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1037 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1069 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1101 | 1 | 1 | 100.00 |
ALWAYS | 1215 | 29 | 29 | 100.00 |
CONT_ASSIGN | 1246 | 1 | 1 | 100.00 |
ALWAYS | 1250 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1290 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1306 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1307 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1311 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1312 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1314 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1318 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1319 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1321 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1322 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1324 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1325 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1327 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1330 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1331 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1333 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1337 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1339 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1340 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1343 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1345 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1346 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1348 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1351 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1352 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1355 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1357 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1360 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1361 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1363 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1364 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1366 | 1 | 1 | 100.00 |
ALWAYS | 1370 | 29 | 29 | 100.00 |
ALWAYS | 1403 | 38 | 38 | 100.00 |
CONT_ASSIGN | 1536 | 0 | 0 | |
CONT_ASSIGN | 1544 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1545 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
223 |
1 |
1 |
238 |
1 |
1 |
254 |
1 |
1 |
430 |
1 |
1 |
551 |
1 |
1 |
877 |
1 |
1 |
909 |
1 |
1 |
941 |
1 |
1 |
973 |
1 |
1 |
1005 |
1 |
1 |
1037 |
1 |
1 |
1069 |
1 |
1 |
1101 |
1 |
1 |
1215 |
1 |
1 |
1216 |
1 |
1 |
1217 |
1 |
1 |
1218 |
1 |
1 |
1219 |
1 |
1 |
1220 |
1 |
1 |
1221 |
1 |
1 |
1222 |
1 |
1 |
1223 |
1 |
1 |
1224 |
1 |
1 |
1225 |
1 |
1 |
1226 |
1 |
1 |
1227 |
1 |
1 |
1228 |
1 |
1 |
1229 |
1 |
1 |
1230 |
1 |
1 |
1231 |
1 |
1 |
1232 |
1 |
1 |
1233 |
1 |
1 |
1234 |
1 |
1 |
1235 |
1 |
1 |
1236 |
1 |
1 |
1237 |
1 |
1 |
1238 |
1 |
1 |
1239 |
1 |
1 |
1240 |
1 |
1 |
1241 |
1 |
1 |
1242 |
1 |
1 |
1243 |
1 |
1 |
1246 |
1 |
1 |
1250 |
1 |
1 |
1282 |
1 |
1 |
1284 |
1 |
1 |
1286 |
1 |
1 |
1287 |
1 |
1 |
1289 |
1 |
1 |
1290 |
1 |
1 |
1292 |
1 |
1 |
1294 |
1 |
1 |
1296 |
1 |
1 |
1298 |
1 |
1 |
1299 |
1 |
1 |
1301 |
1 |
1 |
1302 |
1 |
1 |
1304 |
1 |
1 |
1306 |
1 |
1 |
1307 |
1 |
1 |
1308 |
1 |
1 |
1309 |
1 |
1 |
1311 |
1 |
1 |
1312 |
1 |
1 |
1314 |
1 |
1 |
1316 |
1 |
1 |
1317 |
1 |
1 |
1318 |
1 |
1 |
1319 |
1 |
1 |
1321 |
1 |
1 |
1322 |
1 |
1 |
1324 |
1 |
1 |
1325 |
1 |
1 |
1327 |
1 |
1 |
1328 |
1 |
1 |
1330 |
1 |
1 |
1331 |
1 |
1 |
1333 |
1 |
1 |
1334 |
1 |
1 |
1336 |
1 |
1 |
1337 |
1 |
1 |
1339 |
1 |
1 |
1340 |
1 |
1 |
1342 |
1 |
1 |
1343 |
1 |
1 |
1345 |
1 |
1 |
1346 |
1 |
1 |
1348 |
1 |
1 |
1349 |
1 |
1 |
1351 |
1 |
1 |
1352 |
1 |
1 |
1354 |
1 |
1 |
1355 |
1 |
1 |
1357 |
1 |
1 |
1358 |
1 |
1 |
1360 |
1 |
1 |
1361 |
1 |
1 |
1363 |
1 |
1 |
1364 |
1 |
1 |
1366 |
1 |
1 |
1370 |
1 |
1 |
1371 |
1 |
1 |
1372 |
1 |
1 |
1373 |
1 |
1 |
1374 |
1 |
1 |
1375 |
1 |
1 |
1376 |
1 |
1 |
1377 |
1 |
1 |
1378 |
1 |
1 |
1379 |
1 |
1 |
1380 |
1 |
1 |
1381 |
1 |
1 |
1382 |
1 |
1 |
1383 |
1 |
1 |
1384 |
1 |
1 |
1385 |
1 |
1 |
1386 |
1 |
1 |
1387 |
1 |
1 |
1388 |
1 |
1 |
1389 |
1 |
1 |
1390 |
1 |
1 |
1391 |
1 |
1 |
1392 |
1 |
1 |
1393 |
1 |
1 |
1394 |
1 |
1 |
1395 |
1 |
1 |
1396 |
1 |
1 |
1397 |
1 |
1 |
1398 |
1 |
1 |
1403 |
1 |
1 |
1404 |
1 |
1 |
1406 |
1 |
1 |
1407 |
1 |
1 |
1411 |
1 |
1 |
1415 |
1 |
1 |
1416 |
1 |
1 |
1417 |
1 |
1 |
1418 |
1 |
1 |
1422 |
1 |
1 |
1426 |
1 |
1 |
1427 |
1 |
1 |
1431 |
1 |
1 |
1435 |
1 |
1 |
1439 |
1 |
1 |
1443 |
1 |
1 |
1444 |
1 |
1 |
1448 |
1 |
1 |
1452 |
1 |
1 |
1456 |
1 |
1 |
1460 |
1 |
1 |
1464 |
1 |
1 |
1468 |
1 |
1 |
1472 |
1 |
1 |
1476 |
1 |
1 |
1480 |
1 |
1 |
1484 |
1 |
1 |
1488 |
1 |
1 |
1492 |
1 |
1 |
1496 |
1 |
1 |
1500 |
1 |
1 |
1504 |
1 |
1 |
1508 |
1 |
1 |
1512 |
1 |
1 |
1516 |
1 |
1 |
1520 |
1 |
1 |
1521 |
1 |
1 |
1522 |
1 |
1 |
1536 |
|
unreachable |
1544 |
1 |
1 |
1545 |
1 |
1 |
Cond Coverage for Module :
rstmgr_reg_top
| Total | Covered | Percent |
Conditions | 329 | 329 | 100.00 |
Logical | 329 | 329 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T67,T64,T66 |
1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T21,T57,T68 |
1 | 0 | Covered | T63,T65,T95 |
LINE 79
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T21,T57,T68 |
0 | 1 | 0 | Covered | T63,T65,T95 |
1 | 0 | 0 | Covered | T21,T57,T63 |
LINE 121
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T63,T65,T95 |
0 | 1 | 0 | Covered | T67,T64,T66 |
1 | 0 | 0 | Covered | T67,T64,T66 |
LINE 430
EXPRESSION (alert_info_ctrl_we & alert_regwen_qs)
---------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T63,T65,T66 |
1 | 1 | Covered | T1,T2,T3 |
LINE 551
EXPRESSION (cpu_info_ctrl_we & cpu_regwen_qs)
--------1------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T63,T65,T110 |
1 | 1 | Covered | T1,T2,T3 |
LINE 877
EXPRESSION (sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T3,T12 |
LINE 909
EXPRESSION (sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T3,T12 |
LINE 941
EXPRESSION (sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T3,T12,T24 |
LINE 973
EXPRESSION (sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T3,T12,T24 |
LINE 1005
EXPRESSION (sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T3,T12 |
LINE 1037
EXPRESSION (sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T3,T12 |
LINE 1069
EXPRESSION (sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T3,T12,T24 |
LINE 1101
EXPRESSION (sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T3,T12 |
LINE 1216
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_TEST_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T6 |
LINE 1217
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_REQ_OFFSET)
--------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1218
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_INFO_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1219
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_REGWEN_OFFSET)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T21 |
LINE 1220
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_CTRL_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1221
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_ATTR_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T21 |
LINE 1222
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1223
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_REGWEN_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T21 |
LINE 1224
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_CTRL_OFFSET)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1225
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_ATTR_OFFSET)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T21 |
LINE 1226
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1227
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_0_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1228
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_1_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1229
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_2_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1230
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_3_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1231
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_4_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1232
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_5_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1233
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_6_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1234
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_7_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 1235
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_0_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1236
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_1_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1237
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_2_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1238
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_3_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1239
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_4_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1240
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_5_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1241
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_6_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1242
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_7_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1243
EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ERR_CODE_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T21 |
LINE 1246
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1246
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 1250
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be)))))))
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T67,T63,T64 |
LINE 1250
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1 | Status | Tests |
ALL ZEROS | Covered | T1,T2,T3 |
28 (addr_hit[27] & ((|(4'... | Covered | T2,T7,T21 |
27 (addr_hit[26] & ((|(4'... | Covered | T1,T2,T3 |
26 (addr_hit[25] & ((|(4'... | Covered | T1,T2,T3 |
25 (addr_hit[24] & ((|(4'... | Covered | T1,T2,T3 |
24 (addr_hit[23] & ((|(4'... | Covered | T1,T2,T3 |
23 (addr_hit[22] & ((|(4'... | Covered | T1,T2,T3 |
22 (addr_hit[21] & ((|(4'... | Covered | T1,T2,T3 |
21 (addr_hit[20] & ((|(4'... | Covered | T1,T2,T3 |
20 (addr_hit[19] & ((|(4'... | Covered | T1,T2,T3 |
19 (addr_hit[18] & ((|(4'... | Covered | T1,T2,T7 |
18 (addr_hit[17] & ((|(4'... | Covered | T1,T2,T7 |
17 (addr_hit[16] & ((|(4'... | Covered | T1,T2,T7 |
16 (addr_hit[15] & ((|(4'... | Covered | T1,T2,T7 |
15 (addr_hit[14] & ((|(4'... | Covered | T1,T2,T7 |
14 (addr_hit[13] & ((|(4'... | Covered | T1,T2,T7 |
13 (addr_hit[12] & ((|(4'... | Covered | T1,T2,T7 |
12 (addr_hit[11] & ((|(4'... | Covered | T1,T2,T7 |
11 (addr_hit[10] & ((|(4'... | Covered | T1,T2,T7 |
10 (addr_hit[9] & ((|(4'b... | Covered | T2,T7,T21 |
9 (addr_hit[8] & ((|(4'b... | Covered | T2,T7,T21 |
8 (addr_hit[7] & ((|(4'b... | Covered | T2,T7,T21 |
7 (addr_hit[6] & ((|(4'b... | Covered | T1,T2,T7 |
6 (addr_hit[5] & ((|(4'b... | Covered | T2,T7,T21 |
5 (addr_hit[4] & ((|(4'b... | Covered | T2,T7,T21 |
4 (addr_hit[3] & ((|(4'b... | Covered | T2,T7,T21 |
3 (addr_hit[2] & ((|(4'b... | Covered | T1,T2,T3 |
2 (addr_hit[1] & ((|(4'b... | Covered | T2,T7,T21 |
1 (addr_hit[0] & ((|(4'b... | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T6 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T21 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T21 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T21 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T21 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1250
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 1250
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1250
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T21 |
1 | 1 | Covered | T2,T7,T21 |
LINE 1282
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T4,T6 |
1 | 1 | 0 | Covered | T67,T66,T89 |
1 | 1 | 1 | Covered | T4,T6,T10 |
LINE 1287
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T66,T86,T87 |
1 | 1 | 1 | Covered | T1,T2,T7 |
LINE 1290
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T66,T87 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1299
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T7,T21 |
1 | 1 | 0 | Covered | T67,T63,T64 |
1 | 1 | 1 | Covered | T63,T64,T65 |
LINE 1302
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T63,T64,T65 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1307
EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T7,T21 |
1 | 1 | 0 | Covered | T65,T96,T121 |
1 | 1 | 1 | Covered | T2,T7,T22 |
LINE 1308
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T122,T123,T124 |
1 | 1 | 1 | Covered | T1,T2,T7 |
LINE 1309
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T7,T21 |
1 | 1 | 0 | Covered | T67,T63,T64 |
1 | 1 | 1 | Covered | T63,T64,T65 |
LINE 1312
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T87,T88 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1317
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T7,T21 |
1 | 1 | 0 | Covered | T125,T122 |
1 | 1 | 1 | Covered | T2,T7,T22 |
LINE 1318
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T125,T126,T124 |
1 | 1 | 1 | Covered | T1,T2,T7 |
LINE 1319
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T87 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1322
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T64,T87,T89 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1325
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T65 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1328
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T87 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1331
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T87 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1334
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T86,T87,T89 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1337
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T95 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1340
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T7 |
1 | 1 | 0 | Covered | T67,T64,T86 |
1 | 1 | 1 | Covered | T1,T60,T61 |
LINE 1343
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T89,T127 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1346
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T64,T88 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1349
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T64,T66,T87 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1352
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T64,T87 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1355
EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T87,T89,T90 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1358
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T64,T66 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1361
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T64,T65 |
1 | 1 | 1 | Covered | T1,T3,T12 |
LINE 1364
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T67,T66,T87 |
1 | 1 | 1 | Covered | T1,T3,T12 |
Branch Coverage for Module :
rstmgr_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
34 |
34 |
100.00 |
TERNARY |
1246 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
CASE |
1404 |
29 |
29 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 1246 ((reg_re || reg_we)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if ((intg_err || reg_we_err))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T21,T57,T63 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1404 case (1'b1)
Branches:
-1- | Status | Tests |
addr_hit[0] |
Covered |
T1,T2,T3 |
addr_hit[1] |
Covered |
T1,T2,T3 |
addr_hit[2] |
Covered |
T1,T2,T3 |
addr_hit[3] |
Covered |
T1,T2,T3 |
addr_hit[4] |
Covered |
T1,T2,T3 |
addr_hit[5] |
Covered |
T1,T2,T3 |
addr_hit[6] |
Covered |
T1,T2,T3 |
addr_hit[7] |
Covered |
T1,T2,T3 |
addr_hit[8] |
Covered |
T1,T2,T3 |
addr_hit[9] |
Covered |
T1,T2,T3 |
addr_hit[10] |
Covered |
T1,T2,T3 |
addr_hit[11] |
Covered |
T1,T2,T3 |
addr_hit[12] |
Covered |
T1,T2,T3 |
addr_hit[13] |
Covered |
T1,T2,T3 |
addr_hit[14] |
Covered |
T1,T2,T3 |
addr_hit[15] |
Covered |
T1,T2,T3 |
addr_hit[16] |
Covered |
T1,T2,T3 |
addr_hit[17] |
Covered |
T1,T2,T3 |
addr_hit[18] |
Covered |
T1,T2,T3 |
addr_hit[19] |
Covered |
T1,T2,T3 |
addr_hit[20] |
Covered |
T1,T2,T3 |
addr_hit[21] |
Covered |
T1,T2,T3 |
addr_hit[22] |
Covered |
T1,T2,T3 |
addr_hit[23] |
Covered |
T1,T2,T3 |
addr_hit[24] |
Covered |
T1,T2,T3 |
addr_hit[25] |
Covered |
T1,T2,T3 |
addr_hit[26] |
Covered |
T1,T2,T3 |
addr_hit[27] |
Covered |
T1,T2,T3 |
default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rstmgr_reg_top
Assertion Details
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12383560 |
1009738 |
0 |
0 |
T1 |
5749 |
379 |
0 |
0 |
T2 |
31342 |
3028 |
0 |
0 |
T3 |
2638 |
148 |
0 |
0 |
T4 |
1690 |
31 |
0 |
0 |
T5 |
2842 |
1 |
0 |
0 |
T6 |
1615 |
20 |
0 |
0 |
T7 |
35484 |
2690 |
0 |
0 |
T8 |
42227 |
3200 |
0 |
0 |
T9 |
3518 |
1 |
0 |
0 |
T10 |
1569 |
10 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12383560 |
1009594 |
0 |
0 |
T1 |
5749 |
379 |
0 |
0 |
T2 |
31342 |
3028 |
0 |
0 |
T3 |
2638 |
147 |
0 |
0 |
T4 |
1690 |
31 |
0 |
0 |
T5 |
2842 |
1 |
0 |
0 |
T6 |
1615 |
20 |
0 |
0 |
T7 |
35484 |
2690 |
0 |
0 |
T8 |
42227 |
3200 |
0 |
0 |
T9 |
3518 |
1 |
0 |
0 |
T10 |
1569 |
10 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12383560 |
541828 |
0 |
0 |
T1 |
5749 |
186 |
0 |
0 |
T2 |
31342 |
1666 |
0 |
0 |
T3 |
2638 |
72 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
1 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
1530 |
0 |
0 |
T8 |
42227 |
1500 |
0 |
0 |
T9 |
3518 |
1 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
99 |
0 |
0 |
T12 |
0 |
107 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12383560 |
467766 |
0 |
0 |
T1 |
5749 |
193 |
0 |
0 |
T2 |
31342 |
1362 |
0 |
0 |
T3 |
2638 |
75 |
0 |
0 |
T4 |
1690 |
31 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
20 |
0 |
0 |
T7 |
35484 |
1160 |
0 |
0 |
T8 |
42227 |
1700 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
10 |
0 |
0 |
T11 |
0 |
113 |
0 |
0 |
T12 |
0 |
114 |
0 |
0 |