Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12383560	7508	0	0
alert_regwen_rd_A	12383560	4791	0	0
cpu_regwen_rd_A	12383560	4714	0	0
sw_rst_ctrl_n_0_rd_A	12383560	9519	0	0
sw_rst_ctrl_n_1_rd_A	12383560	9623	0	0
sw_rst_ctrl_n_2_rd_A	12383560	9331	0	0
sw_rst_ctrl_n_3_rd_A	12383560	9747	0	0
sw_rst_ctrl_n_4_rd_A	12383560	9401	0	0
sw_rst_ctrl_n_5_rd_A	12383560	9672	0	0
sw_rst_ctrl_n_6_rd_A	12383560	9547	0	0
sw_rst_ctrl_n_7_rd_A	12383560	9528	0	0
sw_rst_regwen_0_rd_A	12383560	5220	0	0
sw_rst_regwen_1_rd_A	12383560	5195	0	0
sw_rst_regwen_2_rd_A	12383560	5158	0	0
sw_rst_regwen_3_rd_A	12383560	5204	0	0
sw_rst_regwen_4_rd_A	12383560	5230	0	0
sw_rst_regwen_5_rd_A	12383560	5090	0	0
sw_rst_regwen_6_rd_A	12383560	5159	0	0
sw_rst_regwen_7_rd_A	12383560	5211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	7508	0	0
T63	11036	1	0	0
T64	2651	129	0	0
T66	2525	96	0	0
T67	6819	343	0	0
T86	17898	1	0	0
T87	4198	474	0	0
T88	3617	63	0	0
T95	10217	2	0	0
T96	9364	1	0	0
T128	3001	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	4791	0	0
T7	35484	54	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T11	4044	0	0	0
T12	2243	0	0	0
T13	5251	0	0	0
T21	378832	0	0	0
T22	38996	53	0	0
T23	26203	0	0	0
T63	0	29	0	0
T65	0	49	0	0
T72	0	58	0	0
T83	0	192	0	0
T100	0	25	0	0
T101	0	57	0	0
T103	0	5	0	0
T104	0	36	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	4714	0	0
T7	35484	16	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T11	4044	0	0	0
T12	2243	0	0	0
T13	5251	0	0	0
T21	378832	0	0	0
T22	38996	57	0	0
T23	26203	0	0	0
T63	0	5	0	0
T65	0	35	0	0
T72	0	66	0	0
T83	0	280	0	0
T100	0	39	0	0
T101	0	36	0	0
T103	0	5	0	0
T104	0	23	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9519	0	0
T1	5749	5	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	12	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	58	0	0
T51	0	6	0	0
T54	0	10	0	0
T72	0	67	0	0
T80	0	44	0	0
T83	0	399	0	0
T129	0	73	0	0
T130	0	128	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9623	0	0
T1	5749	22	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	41	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	37	0	0
T51	0	20	0	0
T54	0	15	0	0
T72	0	71	0	0
T80	0	40	0	0
T83	0	429	0	0
T129	0	68	0	0
T130	0	142	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9331	0	0
T1	5749	6	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	34	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	75	0	0
T51	0	15	0	0
T54	0	12	0	0
T72	0	79	0	0
T80	0	46	0	0
T83	0	411	0	0
T129	0	58	0	0
T130	0	137	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9747	0	0
T1	5749	16	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	37	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	30	0	0
T51	0	5	0	0
T54	0	7	0	0
T72	0	63	0	0
T80	0	44	0	0
T83	0	401	0	0
T129	0	61	0	0
T130	0	123	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9401	0	0
T1	5749	14	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	35	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	45	0	0
T51	0	7	0	0
T54	0	7	0	0
T72	0	69	0	0
T80	0	31	0	0
T83	0	415	0	0
T129	0	63	0	0
T130	0	128	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9672	0	0
T1	5749	8	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	24	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	51	0	0
T51	0	17	0	0
T54	0	4	0	0
T72	0	60	0	0
T80	0	52	0	0
T83	0	392	0	0
T129	0	52	0	0
T130	0	146	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9547	0	0
T1	5749	10	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	26	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	64	0	0
T51	0	14	0	0
T54	0	8	0	0
T72	0	65	0	0
T80	0	45	0	0
T83	0	434	0	0
T129	0	55	0	0
T130	0	151	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	9528	0	0
T1	5749	18	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	59	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	63	0	0
T51	0	10	0	0
T54	0	9	0	0
T72	0	52	0	0
T80	0	48	0	0
T83	0	478	0	0
T129	0	57	0	0
T130	0	145	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5220	0	0
T1	5749	5	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	39	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	47	0	0
T51	0	1	0	0
T54	0	2	0	0
T72	0	57	0	0
T83	0	258	0	0
T100	0	17	0	0
T101	0	42	0	0
T130	0	28	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5195	0	0
T1	5749	4	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	48	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	42	0	0
T37	0	6	0	0
T54	0	1	0	0
T72	0	71	0	0
T83	0	253	0	0
T100	0	30	0	0
T101	0	44	0	0
T130	0	31	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5158	0	0
T1	5749	5	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	41	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	63	0	0
T51	0	7	0	0
T54	0	6	0	0
T72	0	57	0	0
T83	0	266	0	0
T100	0	46	0	0
T101	0	60	0	0
T130	0	27	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5204	0	0
T1	5749	6	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	42	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	46	0	0
T37	0	4	0	0
T51	0	9	0	0
T72	0	70	0	0
T83	0	229	0	0
T100	0	48	0	0
T101	0	50	0	0
T130	0	25	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5230	0	0
T1	5749	5	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	56	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	42	0	0
T37	0	5	0	0
T54	0	6	0	0
T72	0	54	0	0
T83	0	315	0	0
T100	0	22	0	0
T101	0	54	0	0
T130	0	24	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5090	0	0
T1	5749	9	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	17	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	36	0	0
T37	0	14	0	0
T54	0	9	0	0
T72	0	71	0	0
T83	0	232	0	0
T100	0	26	0	0
T101	0	62	0	0
T130	0	36	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5159	0	0
T1	5749	9	0	0
T2	31342	0	0	0
T3	2638	0	0	0
T4	1690	0	0	0
T5	2842	0	0	0
T6	1615	0	0	0
T7	35484	34	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T22	0	54	0	0
T37	0	7	0	0
T51	0	6	0	0
T72	0	53	0	0
T83	0	275	0	0
T100	0	41	0	0
T101	0	47	0	0
T130	0	26	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12383560	5211	0	0
T7	35484	17	0	0
T8	42227	0	0	0
T9	3518	0	0	0
T10	1569	0	0	0
T11	4044	0	0	0
T12	2243	0	0	0
T13	5251	0	0	0
T21	378832	0	0	0
T22	38996	38	0	0
T23	26203	0	0	0
T37	0	4	0	0
T51	0	6	0	0
T54	0	3	0	0
T72	0	75	0	0
T83	0	298	0	0
T100	0	42	0	0
T101	0	53	0	0
T130	0	31	0	0