Module Definition
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Module : pwrmgr_rstmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.pwrmgr_rstmgr_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pwrmgr_rstmgr_sva_if
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS3311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1


Cond Coverage for Module : pwrmgr_rstmgr_sva_if
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T5

Assert Coverage for Module : pwrmgr_rstmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A 11680055 13414 0 0
gen_assertions_per_power_domains[0].LcHandshakeOn_A 11680055 123597 0 0
gen_assertions_per_power_domains[0].SysHandshakeOff_A 11680055 6752868 0 0
gen_assertions_per_power_domains[0].SysHandshakeOn_A 11680055 197732 0 0
gen_assertions_per_power_domains[1].LcHandshakeOff_A 11680055 13414 0 0
gen_assertions_per_power_domains[1].LcHandshakeOn_A 11680055 123597 0 0
gen_assertions_per_power_domains[1].SysHandshakeOff_A 11680055 6752868 0 0
gen_assertions_per_power_domains[1].SysHandshakeOn_A 11680055 197732 0 0


gen_assertions_per_power_domains[0].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 13414 0 0
T1 5749 4 0 0
T2 31342 43 0 0
T3 2638 8 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 32 0 0
T8 42227 75 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 4 0 0
T12 0 11 0 0
T22 0 37 0 0
T23 0 75 0 0
T24 0 8 0 0

gen_assertions_per_power_domains[0].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 123597 0 0
T1 5749 38 0 0
T2 31342 398 0 0
T3 2638 72 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 289 0 0
T8 42227 706 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 37 0 0
T12 0 99 0 0
T22 0 334 0 0
T23 0 719 0 0
T24 0 72 0 0

gen_assertions_per_power_domains[0].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6752868 0 0
T1 5749 4750 0 0
T2 31342 23110 0 0
T3 2638 1933 0 0
T4 1690 1087 0 0
T5 2842 608 0 0
T6 1615 1048 0 0
T7 35484 25925 0 0
T8 42227 24874 0 0
T9 3518 865 0 0
T10 1569 947 0 0

gen_assertions_per_power_domains[0].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 197732 0 0
T1 5749 58 0 0
T2 31342 630 0 0
T3 2638 104 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 459 0 0
T8 42227 1176 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 68 0 0
T12 0 156 0 0
T22 0 494 0 0
T23 0 1142 0 0
T24 0 126 0 0

gen_assertions_per_power_domains[1].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 13414 0 0
T1 5749 4 0 0
T2 31342 43 0 0
T3 2638 8 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 32 0 0
T8 42227 75 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 4 0 0
T12 0 11 0 0
T22 0 37 0 0
T23 0 75 0 0
T24 0 8 0 0

gen_assertions_per_power_domains[1].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 123597 0 0
T1 5749 38 0 0
T2 31342 398 0 0
T3 2638 72 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 289 0 0
T8 42227 706 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 37 0 0
T12 0 99 0 0
T22 0 334 0 0
T23 0 719 0 0
T24 0 72 0 0

gen_assertions_per_power_domains[1].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 6752868 0 0
T1 5749 4750 0 0
T2 31342 23110 0 0
T3 2638 1933 0 0
T4 1690 1087 0 0
T5 2842 608 0 0
T6 1615 1048 0 0
T7 35484 25925 0 0
T8 42227 24874 0 0
T9 3518 865 0 0
T10 1569 947 0 0

gen_assertions_per_power_domains[1].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11680055 197732 0 0
T1 5749 58 0 0
T2 31342 630 0 0
T3 2638 104 0 0
T4 1690 0 0 0
T5 2842 0 0 0
T6 1615 0 0 0
T7 35484 459 0 0
T8 42227 1176 0 0
T9 3518 0 0 0
T10 1569 0 0 0
T11 0 68 0 0
T12 0 156 0 0
T22 0 494 0 0
T23 0 1142 0 0
T24 0 126 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%