Line Coverage for Module :
pwrmgr_rstmgr_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 33 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
Cond Coverage for Module :
pwrmgr_rstmgr_sva_if
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (((!rst_slow_ni)) || disable_sva)
--------1------- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T5 |
Assert Coverage for Module :
pwrmgr_rstmgr_sva_if
Assertion Details
gen_assertions_per_power_domains[0].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
13414 |
0 |
0 |
T1 |
5749 |
4 |
0 |
0 |
T2 |
31342 |
43 |
0 |
0 |
T3 |
2638 |
8 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
32 |
0 |
0 |
T8 |
42227 |
75 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T22 |
0 |
37 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
gen_assertions_per_power_domains[0].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
123597 |
0 |
0 |
T1 |
5749 |
38 |
0 |
0 |
T2 |
31342 |
398 |
0 |
0 |
T3 |
2638 |
72 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
289 |
0 |
0 |
T8 |
42227 |
706 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
37 |
0 |
0 |
T12 |
0 |
99 |
0 |
0 |
T22 |
0 |
334 |
0 |
0 |
T23 |
0 |
719 |
0 |
0 |
T24 |
0 |
72 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
6752868 |
0 |
0 |
T1 |
5749 |
4750 |
0 |
0 |
T2 |
31342 |
23110 |
0 |
0 |
T3 |
2638 |
1933 |
0 |
0 |
T4 |
1690 |
1087 |
0 |
0 |
T5 |
2842 |
608 |
0 |
0 |
T6 |
1615 |
1048 |
0 |
0 |
T7 |
35484 |
25925 |
0 |
0 |
T8 |
42227 |
24874 |
0 |
0 |
T9 |
3518 |
865 |
0 |
0 |
T10 |
1569 |
947 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
197732 |
0 |
0 |
T1 |
5749 |
58 |
0 |
0 |
T2 |
31342 |
630 |
0 |
0 |
T3 |
2638 |
104 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
459 |
0 |
0 |
T8 |
42227 |
1176 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
68 |
0 |
0 |
T12 |
0 |
156 |
0 |
0 |
T22 |
0 |
494 |
0 |
0 |
T23 |
0 |
1142 |
0 |
0 |
T24 |
0 |
126 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
13414 |
0 |
0 |
T1 |
5749 |
4 |
0 |
0 |
T2 |
31342 |
43 |
0 |
0 |
T3 |
2638 |
8 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
32 |
0 |
0 |
T8 |
42227 |
75 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T22 |
0 |
37 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
123597 |
0 |
0 |
T1 |
5749 |
38 |
0 |
0 |
T2 |
31342 |
398 |
0 |
0 |
T3 |
2638 |
72 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
289 |
0 |
0 |
T8 |
42227 |
706 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
37 |
0 |
0 |
T12 |
0 |
99 |
0 |
0 |
T22 |
0 |
334 |
0 |
0 |
T23 |
0 |
719 |
0 |
0 |
T24 |
0 |
72 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
6752868 |
0 |
0 |
T1 |
5749 |
4750 |
0 |
0 |
T2 |
31342 |
23110 |
0 |
0 |
T3 |
2638 |
1933 |
0 |
0 |
T4 |
1690 |
1087 |
0 |
0 |
T5 |
2842 |
608 |
0 |
0 |
T6 |
1615 |
1048 |
0 |
0 |
T7 |
35484 |
25925 |
0 |
0 |
T8 |
42227 |
24874 |
0 |
0 |
T9 |
3518 |
865 |
0 |
0 |
T10 |
1569 |
947 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11680055 |
197732 |
0 |
0 |
T1 |
5749 |
58 |
0 |
0 |
T2 |
31342 |
630 |
0 |
0 |
T3 |
2638 |
104 |
0 |
0 |
T4 |
1690 |
0 |
0 |
0 |
T5 |
2842 |
0 |
0 |
0 |
T6 |
1615 |
0 |
0 |
0 |
T7 |
35484 |
459 |
0 |
0 |
T8 |
42227 |
1176 |
0 |
0 |
T9 |
3518 |
0 |
0 |
0 |
T10 |
1569 |
0 |
0 |
0 |
T11 |
0 |
68 |
0 |
0 |
T12 |
0 |
156 |
0 |
0 |
T22 |
0 |
494 |
0 |
0 |
T23 |
0 |
1142 |
0 |
0 |
T24 |
0 |
126 |
0 |
0 |