SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_alert_info | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.u_cpu_info | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 7 | 100.00 | |
ALWAYS | 32 | 4 | 4 | 100.00 |
ALWAYS | 40 | 2 | 2 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
33 | 1 | 1 | |
34 | 1 | 1 | |
35 | 1 | 1 | |
MISSING_ELSE | |||
40 | 1 | 1 | |
41 | 1 | 1 | |
44 | unreachable | ||
45 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 7 | 100.00 | |
ALWAYS | 32 | 4 | 4 | 100.00 |
ALWAYS | 40 | 2 | 2 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
33 | 1 | 1 | |
34 | 1 | 1 | |
35 | 1 | 1 | |
MISSING_ELSE | |||
40 | 1 | 1 | |
41 | 1 | 1 | |
44 | unreachable | ||
45 | 1 | 1 | |
51 | unreachable |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 32 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
CntStoreSlot_A | 1006 | 1006 | 0 | 0 |
CntWidth_A | 1006 | 1006 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1006 | 1006 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1006 | 1006 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 7 | 100.00 | |
ALWAYS | 32 | 4 | 4 | 100.00 |
ALWAYS | 40 | 2 | 2 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
33 | 1 | 1 | |
34 | 1 | 1 | |
35 | 1 | 1 | |
MISSING_ELSE | |||
40 | 1 | 1 | |
41 | 1 | 1 | |
44 | unreachable | ||
45 | 1 | 1 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 32 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
CntStoreSlot_A | 503 | 503 | 0 | 0 |
CntWidth_A | 503 | 503 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 7 | 100.00 | |
ALWAYS | 32 | 4 | 4 | 100.00 |
ALWAYS | 40 | 2 | 2 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
32 | 1 | 1 | |
33 | 1 | 1 | |
34 | 1 | 1 | |
35 | 1 | 1 | |
MISSING_ELSE | |||
40 | 1 | 1 | |
41 | 1 | 1 | |
44 | unreachable | ||
45 | 1 | 1 | |
51 | unreachable |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 32 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
CntStoreSlot_A | 503 | 503 | 0 | 0 |
CntWidth_A | 503 | 503 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |