Module Definition
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Module : rstmgr_crash_info
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_info 100.00 100.00 100.00 100.00
tb.dut.u_cpu_info 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_info

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_cpu_info

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : rstmgr_crash_info ( parameter CrashDumpWidth=276,CrashStoreSlot=9,SlotCntWidth=4,TotalWidth=288 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_info

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3244100.00
ALWAYS4022100.00
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
34 1 1
35 1 1
MISSING_ELSE
40 1 1
41 1 1
44 unreachable
45 1 1


Line Coverage for Module : rstmgr_crash_info ( parameter CrashDumpWidth=225,CrashStoreSlot=8,SlotCntWidth=3,TotalWidth=256 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_cpu_info

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3244100.00
ALWAYS4022100.00
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
34 1 1
35 1 1
MISSING_ELSE
40 1 1
41 1 1
44 unreachable
45 1 1
51 unreachable


Branch Coverage for Module : rstmgr_crash_info
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Module : rstmgr_crash_info
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntStoreSlot_A 1006 1006 0 0
CntWidth_A 1006 1006 0 0


CntStoreSlot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1006 1006 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

CntWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1006 1006 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_alert_info
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3244100.00
ALWAYS4022100.00
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
34 1 1
35 1 1
MISSING_ELSE
40 1 1
41 1 1
44 unreachable
45 1 1


Branch Coverage for Instance : tb.dut.u_alert_info
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_alert_info
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntStoreSlot_A 503 503 0 0
CntWidth_A 503 503 0 0


CntStoreSlot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

CntWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_cpu_info
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3244100.00
ALWAYS4022100.00
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
34 1 1
35 1 1
MISSING_ELSE
40 1 1
41 1 1
44 unreachable
45 1 1
51 unreachable


Branch Coverage for Instance : tb.dut.u_cpu_info
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv' or '../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_crash_info.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (dump_capture_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_cpu_info
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntStoreSlot_A 503 503 0 0
CntWidth_A 503 503 0 0


CntStoreSlot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

CntWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503 503 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%