Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T2,T7,T22
1	0	Covered	T1,T2,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55104885	9167	0	0
CascadeEffAonToRstPorAboveRise_A	55104885	9167	0	0
CascadeEffAonToRstPorIoAboveFall_A	52899386	9167	0	0
CascadeEffAonToRstPorIoAboveRise_A	52899386	9167	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26450597	9167	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26450597	9167	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13224784	9167	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13224784	9167	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26450558	9167	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26450558	9167	0	0
CascadeLcToLcAboveFall_A	55104885	22581	0	0
CascadeLcToLcAboveRise_A	55104885	22581	0	0
CascadeLcToLcAonAboveFall_A	1670472	22581	0	0
CascadeLcToLcAonAboveRise_A	1670472	22581	0	0
CascadeLcToLcShadowedAboveFall_A	55104885	22581	0	0
CascadeLcToLcShadowedAboveRise_A	55104885	22581	0	0
CascadePorToAonAboveFall_A	1670472	7172	0	0
CascadeSysToSysAboveFall_A	55104885	22581	0	0
CascadeSysToSysAboveRise_A	55104885	22581	0	0
ScanRstToAonRise_A	1670472	233	0	0
StablePorToAonRise_A	1670472	9167	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11680055	22581	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11680055	22581	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11680055	22581	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11680055	22581	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13224784	22581	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13224784	22581	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11680055	22581	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11680055	22581	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11680055	22581	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11680055	22581	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	9167	0	0
T1	24766	2	0	0
T2	154423	18	0	0
T3	13455	1	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	20	0	0
T8	189034	27	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	9167	0	0
T1	24766	2	0	0
T2	154423	18	0	0
T3	13455	1	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	20	0	0
T8	189034	27	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	9167	0	0
T1	23765	2	0	0
T2	148239	18	0	0
T3	12916	1	0	0
T4	7029	1	0	0
T5	11639	2	0	0
T6	6825	1	0	0
T7	161435	20	0	0
T8	181463	27	0	0
T9	14629	2	0	0
T10	6451	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52899386	9167	0	0
T1	23765	2	0	0
T2	148239	18	0	0
T3	12916	1	0	0
T4	7029	1	0	0
T5	11639	2	0	0
T6	6825	1	0	0
T7	161435	20	0	0
T8	181463	27	0	0
T9	14629	2	0	0
T10	6451	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	9167	0	0
T1	11886	2	0	0
T2	74110	18	0	0
T3	6458	1	0	0
T4	3515	1	0	0
T5	5818	2	0	0
T6	3411	1	0	0
T7	80726	20	0	0
T8	90745	27	0	0
T9	7313	2	0	0
T10	3225	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450597	9167	0	0
T1	11886	2	0	0
T2	74110	18	0	0
T3	6458	1	0	0
T4	3515	1	0	0
T5	5818	2	0	0
T6	3411	1	0	0
T7	80726	20	0	0
T8	90745	27	0	0
T9	7313	2	0	0
T10	3225	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	9167	0	0
T1	5942	2	0	0
T2	37060	18	0	0
T3	3228	1	0	0
T4	1757	1	0	0
T5	2908	2	0	0
T6	1706	1	0	0
T7	40365	20	0	0
T8	45374	27	0	0
T9	3656	2	0	0
T10	1611	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	9167	0	0
T1	5942	2	0	0
T2	37060	18	0	0
T3	3228	1	0	0
T4	1757	1	0	0
T5	2908	2	0	0
T6	1706	1	0	0
T7	40365	20	0	0
T8	45374	27	0	0
T9	3656	2	0	0
T10	1611	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	9167	0	0
T1	11885	2	0	0
T2	74120	18	0	0
T3	6458	1	0	0
T4	3515	1	0	0
T5	5818	2	0	0
T6	3412	1	0	0
T7	80729	20	0	0
T8	90748	27	0	0
T9	7314	2	0	0
T10	3225	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26450558	9167	0	0
T1	11885	2	0	0
T2	74120	18	0	0
T3	6458	1	0	0
T4	3515	1	0	0
T5	5818	2	0	0
T6	3412	1	0	0
T7	80729	20	0	0
T8	90748	27	0	0
T9	7314	2	0	0
T10	3225	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	22581	0	0
T1	742	6	0	0
T2	4731	61	0	0
T3	402	9	0	0
T4	217	1	0	0
T5	363	2	0	0
T6	213	1	0	0
T7	5098	52	0	0
T8	5686	102	0	0
T9	456	2	0	0
T10	200	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	22581	0	0
T1	742	6	0	0
T2	4731	61	0	0
T3	402	9	0	0
T4	217	1	0	0
T5	363	2	0	0
T6	213	1	0	0
T7	5098	52	0	0
T8	5686	102	0	0
T9	456	2	0	0
T10	200	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	7172	0	0
T1	742	1	0	0
T2	4731	8	0	0
T3	402	1	0	0
T4	217	1	0	0
T5	363	7	0	0
T6	213	1	0	0
T7	5098	12	0	0
T8	5686	27	0	0
T9	456	9	0	0
T10	200	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55104885	22581	0	0
T1	24766	6	0	0
T2	154423	61	0	0
T3	13455	9	0	0
T4	7321	1	0	0
T5	12124	2	0	0
T6	7110	1	0	0
T7	168190	52	0	0
T8	189034	102	0	0
T9	15239	2	0	0
T10	6720	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	233	0	0
T2	4731	1	0	0
T3	402	0	0	0
T4	217	0	0	0
T5	363	0	0	0
T6	213	0	0	0
T7	5098	0	0	0
T8	5686	0	0	0
T9	456	0	0	0
T10	200	0	0	0
T21	50598	0	0	0
T48	0	1	0	0
T72	0	3	0	0
T73	0	5	0	0
T82	0	5	0	0
T83	0	8	0	0
T97	0	1	0	0
T100	0	1	0	0
T108	0	1	0	0
T109	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670472	9167	0	0
T1	742	2	0	0
T2	4731	18	0	0
T3	402	1	0	0
T4	217	1	0	0
T5	363	2	0	0
T6	213	1	0	0
T7	5098	20	0	0
T8	5686	27	0	0
T9	456	2	0	0
T10	200	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	22581	0	0
T1	5942	6	0	0
T2	37060	61	0	0
T3	3228	9	0	0
T4	1757	1	0	0
T5	2908	2	0	0
T6	1706	1	0	0
T7	40365	52	0	0
T8	45374	102	0	0
T9	3656	2	0	0
T10	1611	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13224784	22581	0	0
T1	5942	6	0	0
T2	37060	61	0	0
T3	3228	9	0	0
T4	1757	1	0	0
T5	2908	2	0	0
T6	1706	1	0	0
T7	40365	52	0	0
T8	45374	102	0	0
T9	3656	2	0	0
T10	1611	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11680055	22581	0	0
T1	5749	6	0	0
T2	31342	61	0	0
T3	2638	9	0	0
T4	1690	1	0	0
T5	2842	2	0	0
T6	1615	1	0	0
T7	35484	52	0	0
T8	42227	102	0	0
T9	3518	2	0	0
T10	1569	1	0	0