RV_DM Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.600s	822.521us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	0.870s	71.015us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	0.890s	69.841us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	9.510s	2.908ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.300s	370.821us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	2.390s	471.498us	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	4.730s	1.346ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.700m	48.968ms	4	5	80.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.181m	19.348ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	6.920s	2.118ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	3.990s	6.606ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.290s	720.206us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.540s	268.761us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.780s	48.781us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.410s	250.186us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.760s	117.473us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.690s	484.132us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	0.740s	22.565us	1	2	50.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.820s	39.638us	0	2	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.990s	88.839us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.290s	720.206us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.860s	69.743us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.540s	110.001us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.570s	894.162us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	38.590s	15.139ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.304m	13.919ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	9.460s	3.393ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.304m	13.919ms	5	5	100.00
		rv_dm_csr_rw	2.570s	894.162us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.710s	46.845us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.730s	19.200us	5	5	100.00
V1		TOTAL			157	161	97.52
V2	idcode	rv_dm_smoke	2.600s	822.521us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.290s	563.400us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.730s	55.552us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	0.860s	202.798us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	27.430s	6.964ms	19	20	95.00
		rv_dm_delayed_resp_sba_tl_access	28.730s	7.193ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	2.372m	50.000ms	16	20	80.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.429m	50.000ms	10	20	50.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.060s	255.373us	1	2	50.00
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	1.940s	388.762us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.840s	152.588us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.220s	1.637ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.173m	50.000ms	16	40	40.00
V2	stress_all	rv_dm_stress_all	13.990s	4.279ms	13	50	26.00
V2	alert_test	rv_dm_alert_test	0.810s	43.742us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.440s	3.026ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.440s	3.026ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.304m	13.919ms	5	5	100.00
		rv_dm_csr_hw_reset	2.540s	110.001us	5	5	100.00
		rv_dm_csr_rw	2.570s	894.162us	20	20	100.00
		rv_dm_same_csr_outstanding	9.230s	3.687ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.304m	13.919ms	5	5	100.00
		rv_dm_csr_hw_reset	2.540s	110.001us	5	5	100.00
		rv_dm_csr_rw	2.570s	894.162us	20	20	100.00
		rv_dm_same_csr_outstanding	9.230s	3.687ms	20	20	100.00
V2		TOTAL			199	276	72.10
V2S	tl_intg_err	rv_dm_sec_cm	1.540s	170.772us	5	5	100.00
		rv_dm_tl_intg_err	21.170s	1.224ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	29.790s	2.623ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			381	512	74.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	25	89.29
V2	18	16	10	55.56
V2S	10	2	2	20.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.32	94.44	79.92	87.69	78.21	83.66	98.42	39.88

Failure Buckets

UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 50 failures:

Test rv_dm_stress_all has 24 failures.

0.rv_dm_stress_all.81937564499447137256359692334910838009208524090313549326423104454813213467301
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 21257240906 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 21257240906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_stress_all.95943984802596438049083551155196889019947173460909408104029745862997462687778
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 9393884699 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 9393884699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test rv_dm_progbuf_busy has 1 failures.

1.rv_dm_progbuf_busy.56292513877922902002905920409207371765802639369851803955701157494484100963967
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_progbuf_busy/latest/run.log

  UVM_ERROR @  10243156 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  10243156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all_with_rand_reset has 24 failures.

2.rv_dm_stress_all_with_rand_reset.45583336223572089141547147187785142557402371038216974265609840784675527486153
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  32254160 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  32254160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_dm_stress_all_with_rand_reset.59588563468232150745556169054302385431152958215457947015574362620232753379634
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  17018581 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  17018581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test rv_dm_autoincr_sba_tl_access has 1 failures.

18.rv_dm_autoincr_sba_tl_access.88958553534183298464301883675766370053938312199908420539138077444090303017783
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log

  UVM_ERROR @  15583340 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  15583340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
- Test rv_dm_autoincr_sba_tl_access has 9 failures.
  - 0.rv_dm_autoincr_sba_tl_access.101775244880694746114362792710607247442580730790282922072898043561889483564278
    Line 401, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_autoincr_sba_tl_access.77106027000785222725951409598927921961455925345869350167629062486137934936808
    Line 467, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
  - 4.rv_dm_jtag_dmi_csr_bit_bash.44153553560057321892802040439782292117496438224904959879144672396307968623260
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 4 failures.
  - 7.rv_dm_bad_sba_tl_access.1284275303406623916719528356434611832158920216500405427926505789725047778059
    Line 329, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rv_dm_bad_sba_tl_access.23549255422489737689819288000771116874757168283187188104938001252592716799356
    Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 26.rv_dm_tap_fsm_rand_reset.40115761567015080391618786432481995287705053999400039024784623114846985840891
    Line 297, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 12 failures:
- Test rv_dm_tap_fsm_rand_reset has 12 failures.
  - 1.rv_dm_tap_fsm_rand_reset.102026400249503452668234244983997224771401318002792459769127016691266437751352
    Line 343, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 8845055536 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8845055536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_dm_tap_fsm_rand_reset.25022410174219315496945720789471780045317722302606527929284749455610792537037
    Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 7032298112 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7032298112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 8 failures:

Test rv_dm_stress_all_with_rand_reset has 4 failures.

6.rv_dm_stress_all_with_rand_reset.85879373687440333054140317274137564356247268879015999777160216594118945291621
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  66718433 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
  UVM_INFO @  66718433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rv_dm_stress_all_with_rand_reset.15138994986359239556847392688524002576195393602042515672979925159681246571612
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 305609741 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
  UVM_INFO @ 305609741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rv_dm_stress_all has 4 failures.

25.rv_dm_stress_all.70627500759979235845236703358619441001206806140514671770712946810982441283768
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2188879672 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
  UVM_INFO @ 2188879672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.rv_dm_stress_all.79598603303344607390331552852273522007183775763439889247334836893775405243550
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 718615506 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (29142872950 [0x6c90cf376] vs 4209 [0x1071])
  UVM_INFO @ 718615506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 8 failures:
- Test rv_dm_stress_all_with_rand_reset has 7 failures.
  - 7.rv_dm_stress_all_with_rand_reset.32666494934605646254977717944585186308461242840493440774848307584231232891540
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  10936234 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @  10936234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rv_dm_stress_all_with_rand_reset.35352144911184515583473457710876237742485384286310887519450874083625290872478
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  21292345 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @  21292345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
- Test rv_dm_stress_all has 1 failures.
  - 18.rv_dm_stress_all.84358486531156938298225567733588722748882736341258226212991136961833089695708
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @   4785225 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @   4785225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 6 failures:
- Test rv_dm_tap_fsm_rand_reset has 6 failures.
  - 18.rv_dm_tap_fsm_rand_reset.87114731800003869393401051511132656947445865273651026866322793749442466894988
    Line 332, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 5329809975 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5329809975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rv_dm_tap_fsm_rand_reset.99579024536764671609019736389077942000351134823421120767200992630191097165356
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 1979305249 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1979305249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 4 failures:

Test rv_dm_jtag_dmi_debug_disabled has 1 failures.

1.rv_dm_jtag_dmi_debug_disabled.67078739307693261969481042474103919490797371345752741610204953892638346279141
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log

  UVM_ERROR @  16249480 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 2827675256 [0xa88ae678])
  UVM_INFO @  16249480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all_with_rand_reset has 1 failures.

4.rv_dm_stress_all_with_rand_reset.106337717367666997683485343317379087732961584578811378001379786324492062783945
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2241696503 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 4197572384 [0xfa31df20])
  UVM_INFO @ 2241696503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 2 failures.

19.rv_dm_stress_all.45500339237936395153947202764047133891365101202958821604930779828395227482169
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 5278871100 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 4217108300 [0xfb5bf74c])
  UVM_INFO @ 5278871100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rv_dm_stress_all.74583458187313668286309560681805588700622447286867885849065320258218358828260
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2870954407 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3924368318 [0xe9e91bbe])
  UVM_INFO @ 2870954407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 22.rv_dm_stress_all_with_rand_reset.56215918359942429685523491598938338373978110716477994182705079457132725200159
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 242195009 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 242195009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.rv_dm_stress_all_with_rand_reset.73582959020434332338018466854336562268830882570651230959433877286535148682833
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  70705638 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @  70705638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 30.rv_dm_stress_all_with_rand_reset.96891205103078693601554717370919699272075504631832178816726725718758784048688
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 412462143 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 583874873 [0x22cd3939]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 412462143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.rv_dm_stress_all_with_rand_reset.41649024217918663684713547659649774223950979741764495896333352600778590010215
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 642225450 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 4151579633 [0xf77413f1]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 642225450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
- Test rv_dm_abstractcmd_status has 2 failures.
  - 0.rv_dm_abstractcmd_status.19770771578234134771999834414322347948006990548196971017583482158549048237818
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - 1.rv_dm_abstractcmd_status.17547428398249812093337903093150710249409300868036610159576117181594496688771
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 1.rv_dm_stress_all_with_rand_reset.58631964926129754239561485745244694354032570561737842513331666304261852906414
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 758094205 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (11 [0xb] vs 196619 [0x3000b])
  UVM_INFO @ 758094205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rv_dm_stress_all_with_rand_reset.75772276613948112924714549041528962577896899474700316458326368693037378652755
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2623405756 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (24 [0x18] vs 285255192 [0x1100a618])
  UVM_INFO @ 2623405756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 2 failures:
- Test rv_dm_tap_fsm_rand_reset has 2 failures.
  - 8.rv_dm_tap_fsm_rand_reset.35409790038911389334031428825612323185184257554163911936696457123729251348540
    Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 5032491002 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5032491002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rv_dm_tap_fsm_rand_reset.51696544449279212507178591434028225752350384497434970867229426195845107386960
    Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 1047723143 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1047723143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 2 failures:

Test rv_dm_stress_all has 1 failures.

9.rv_dm_stress_all.78809940314540756751329902793573868168642766585531338633252243234584493625927
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log

  UVM_ERROR @   4045939 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0  dr_len: 'h0  ir: 'h0  dr: 'hxxxxxxxxxxxxxxxx  dout: 'hxxxxxxxxxxxxxxxx  bus_op: BusOpWrite  skip_reselected_ir: 'h0  ir_pause_count: 'h0  dr_pause_count: 'h0  }
  . ir_len & dr_len are both zero, or non-zero.
  UVM_INFO @   4045939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_sba_tl_access has 1 failures.

19.rv_dm_sba_tl_access.50863958365633398799849507168511358464899677742987366145789943905600449046198
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest/run.log

  UVM_ERROR @   3751745 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0  dr_len: 'h0  ir: 'h0  dr: 'hxxxxxxxxxxxxxxxx  dout: 'hxxxxxxxxxxxxxxxx  bus_op: BusOpWrite  skip_reselected_ir: 'h0  ir_pause_count: 'h0  dr_pause_count: 'h0  }
  . ir_len & dr_len are both zero, or non-zero.
  UVM_INFO @   3751745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.64594068856580671615418164301436327147393911174880712686814354000506882459284
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  12930851 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  12930851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.2245637193404591288986277046404382624615473883840537009097895003672919148554
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1084713684 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 1084713684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 12.rv_dm_stress_all.33507415814948224370545433461284492598031949817773827777091669349544987379597
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @  70035823 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  70035823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 12.rv_dm_stress_all_with_rand_reset.59151969210755877777882305439465103907995712571155786477733618947203110551361
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  81763608 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
  UVM_INFO @  81763608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 13.rv_dm_tap_fsm_rand_reset.57310701591978985787804738151572898722038218098258737905750639828088510374425
    Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 5493103301 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5493103301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 14.rv_dm_tap_fsm_rand_reset.114763737114965450249896473676293096630324190182362806721391728286006413266182
    Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 3199453819 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
  UVM_INFO @ 3199453819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 16.rv_dm_stress_all_with_rand_reset.86624494499307375220083253092749433987108688844682888574413737144803836198919
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  29741513 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  29741513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 20.rv_dm_stress_all_with_rand_reset.55659327214545281610240735106311426129637324251503836919500919819801245515364
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2337359757 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xd0ff4100)
  UVM_INFO @ 2337359757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.abstractdata_* has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 23.rv_dm_stress_all.64924328269127337129527645882250524753268857345531251591987935219200470410070
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @  18013639 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
  UVM_INFO @  18013639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 31.rv_dm_stress_all.15866069551631346533377502743271575220392469025075289050224131758297195569514
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 107791137 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (1136154817300 [0x108881ab314] vs 0 [0x0])
  UVM_INFO @ 107791137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 38.rv_dm_tap_fsm_rand_reset.88846008645633727191693722297729591792528835703821669248927507915228466757552
    Line 277, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 8888131205 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8888131205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 40.rv_dm_stress_all.41537892817167290072844723624087057790236765231174437141077342529637938143278
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 7324371448 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
  UVM_INFO @ 7324371448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 43.rv_dm_stress_all.6864277181398513981512284365277666965893290346289466787735858537801020294639
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2050006121 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (20 [0x14] vs 2958143569 [0xb051b051])
  UVM_INFO @ 2050006121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```