RV_DM Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.480s 268.371us 1 2 50.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.990s 180.757us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.900s 86.187us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 7.410s 3.887ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.470s 269.232us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 6.090s 1.833ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.630s 2.263ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 52.860s 11.387ms 4 5 80.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 38.500s 12.410ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 12.300s 3.357ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 4.180s 893.920us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.540s 3.696ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.150s 721.226us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.900s 56.649us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.260s 361.425us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.840s 62.170us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.700s 29.247us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 2.480s 579.353us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.860s 62.987us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.940s 175.200us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.540s 3.696ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.840s 34.230us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.540s 252.385us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.550s 1.034ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.093m 5.738ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.372m 28.455ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.530s 3.777ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.372m 28.455ms 5 5 100.00
rv_dm_csr_rw 2.550s 1.034ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.710s 85.508us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 20.006us 5 5 100.00
V1 TOTAL 157 161 97.52
V2 idcode rv_dm_smoke 1.480s 268.371us 1 2 50.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.990s 544.217us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 30.840s 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.870s 239.274us 2 2 100.00
V2 sba rv_dm_sba_tl_access 6.900s 4.984ms 4 20 20.00
rv_dm_delayed_resp_sba_tl_access 1.820s 652.838us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.430s 1.898ms 2 20 10.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 23.520s 50.000ms 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.280s 226.475us 1 2 50.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 2.180s 722.440us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.050s 113.438us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 2.950s 3.039ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 41.340s 11.051ms 13 40 32.50
V2 stress_all rv_dm_stress_all 1.859h 10.000s 6 50 12.00
V2 alert_test rv_dm_alert_test 0.780s 121.837us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.450s 476.812us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.450s 476.812us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.372m 28.455ms 5 5 100.00
rv_dm_csr_hw_reset 2.540s 252.385us 5 5 100.00
rv_dm_csr_rw 2.550s 1.034ms 20 20 100.00
rv_dm_same_csr_outstanding 8.720s 3.680ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.372m 28.455ms 5 5 100.00
rv_dm_csr_hw_reset 2.540s 252.385us 5 5 100.00
rv_dm_csr_rw 2.550s 1.034ms 20 20 100.00
rv_dm_same_csr_outstanding 8.720s 3.680ms 20 20 100.00
V2 TOTAL 128 276 46.38
V2S tl_intg_err rv_dm_sec_cm 1.300s 483.932us 5 5 100.00
rv_dm_tl_intg_err 20.150s 2.035ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 33.590s 2.988ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 310 512 60.55

Testplan Progress

Items Total Written Passing Progress
V1 28 28 25 89.29
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.45 93.96 82.01 87.61 73.08 82.50 98.42 38.60

Failure Buckets

Past Results