RV_DM Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.930s 1.559ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.940s 546.615us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.360s 649.933us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.122m 25.532ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 5.320s 2.855ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 1.008m 24.175ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 25.150s 9.773ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.516m 33.347ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 10.155m 234.060ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 18.270s 23.721ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 42.830s 17.297ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 3.750s 1.087ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.350s 1.230ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.900s 354.848us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.390s 248.830us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.800s 114.630us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.070s 1.174ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 2.370s 622.484us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.170s 265.142us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.430s 259.882us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 3.750s 1.087ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.880s 61.708us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.020s 435.139us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.720s 169.834us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 41.270s 14.730ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.253m 7.185ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.430s 4.076ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.253m 7.185ms 5 5 100.00
rv_dm_csr_rw 2.720s 169.834us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.030s 141.727us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.790s 84.373us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 2.930s 1.559ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.210s 276.416us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.050s 586.688us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.700s 1.554ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 50.170s 19.247ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 30.920s 11.703ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 14.290s 5.372ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.621m 134.454ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 3.500s 1.194ms 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 4.500s 5.094ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.270s 683.986us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 5.450s 5.590ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 2.244m 56.131ms 10 10 100.00
V2 stress_all rv_dm_stress_all 2.748h 10.000s 20 50 40.00
V2 alert_test rv_dm_alert_test 1.080s 163.592us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.490s 959.838us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.490s 959.838us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.253m 7.185ms 5 5 100.00
rv_dm_csr_hw_reset 3.020s 435.139us 5 5 100.00
rv_dm_csr_rw 2.720s 169.834us 20 20 100.00
rv_dm_same_csr_outstanding 8.060s 538.215us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.253m 7.185ms 5 5 100.00
rv_dm_csr_hw_reset 3.020s 435.139us 5 5 100.00
rv_dm_csr_rw 2.720s 169.834us 20 20 100.00
rv_dm_same_csr_outstanding 8.060s 538.215us 20 20 100.00
V2 TOTAL 215 246 87.40
V2S tl_intg_err rv_dm_sec_cm 4.740s 2.832ms 5 5 100.00
rv_dm_tl_intg_err 31.190s 5.713ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 33.200s 6.144ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 416 457 91.03

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 16 14 77.78
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.40 94.61 78.90 88.43 71.79 84.67 98.52 38.91

Failure Buckets

Past Results