RV_DM Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.930s	1.559ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.940s	546.615us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.360s	649.933us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.122m	25.532ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	5.320s	2.855ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	1.008m	24.175ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	25.150s	9.773ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.516m	33.347ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	10.155m	234.060ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	18.270s	23.721ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	42.830s	17.297ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.750s	1.087ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.350s	1.230ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.900s	354.848us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.390s	248.830us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.800s	114.630us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.070s	1.174ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.370s	622.484us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.170s	265.142us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.430s	259.882us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.750s	1.087ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.880s	61.708us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.020s	435.139us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.720s	169.834us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	41.270s	14.730ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.253m	7.185ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.430s	4.076ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.253m	7.185ms	5	5	100.00
		rv_dm_csr_rw	2.720s	169.834us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.030s	141.727us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.790s	84.373us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.930s	1.559ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.210s	276.416us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.050s	586.688us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.700s	1.554ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	50.170s	19.247ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	30.920s	11.703ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	14.290s	5.372ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.621m	134.454ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	3.500s	1.194ms	2	2	100.00
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	4.500s	5.094ms	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.270s	683.986us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.450s	5.590ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	2.244m	56.131ms	10	10	100.00
V2	stress_all	rv_dm_stress_all	2.748h	10.000s	20	50	40.00
V2	alert_test	rv_dm_alert_test	1.080s	163.592us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.490s	959.838us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.490s	959.838us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.253m	7.185ms	5	5	100.00
		rv_dm_csr_hw_reset	3.020s	435.139us	5	5	100.00
		rv_dm_csr_rw	2.720s	169.834us	20	20	100.00
		rv_dm_same_csr_outstanding	8.060s	538.215us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.253m	7.185ms	5	5	100.00
		rv_dm_csr_hw_reset	3.020s	435.139us	5	5	100.00
		rv_dm_csr_rw	2.720s	169.834us	20	20	100.00
		rv_dm_same_csr_outstanding	8.060s	538.215us	20	20	100.00
V2		TOTAL			215	246	87.40
V2S	tl_intg_err	rv_dm_sec_cm	4.740s	2.832ms	5	5	100.00
		rv_dm_tl_intg_err	31.190s	5.713ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	33.200s	6.144ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			416	457	91.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	16	14	77.78
V2S	10	2	2	20.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
79.40	94.61	78.90	88.43	71.79	84.67	98.52	38.91

Failure Buckets

Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rv_dm_stress_all has 15 failures.
  - 1.rv_dm_stress_all.4241033917150279664796268537064595346041076792635745655319101603759774839557
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:39b1c2d6-1b9c-43b8-9982-23cce00e46ee
```
  - 5.rv_dm_stress_all.105199500532179863807014767067175050955756774370757433707994699982379359276018
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:9443a46b-1537-467b-bed1-f8138915124b
```
  - ... and 13 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 11 failures:
- Test rv_dm_stress_all has 11 failures.
  - 0.rv_dm_stress_all.89651313078123839283871240682488230798721343058367557905489235340031599158477
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rv_dm_stress_all.39556115208302671840093184559544263236638106129396227315126247051345032246527
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:208) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 3.rv_dm_stress_all_with_rand_reset.36651755948255889416304646764256686195402675337520293295611579534188326081013
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1942234529 ps: (rv_dm_base_vseq.sv:208) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 1942234529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.84780552757603114684392378419081020808932662841499509354608994321402356951002
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 622525538 ps: (rv_dm_base_vseq.sv:208) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 4 [0x4])
  UVM_INFO @ 622525538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

5.rv_dm_stress_all_with_rand_reset.21372613462012260372065233593608630640259238502475239014389061194349418547788
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1495149004 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (22 [0x16] vs 2634022958 [0x9d00002e])
  UVM_INFO @ 1495149004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.rv_dm_stress_all_with_rand_reset.4638543449617129780068358989265712875699438603916394829955399299709918479924
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6144206958 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (25 [0x19] vs 4019 [0xfb3])
  UVM_INFO @ 6144206958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 1 failures.

14.rv_dm_stress_all.3954399719701270151748801011492046027563114697413737443598166819725210805146
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 16048154023 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 2958143569 [0xb051b051])
  UVM_INFO @ 16048154023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 0.rv_dm_stress_all_with_rand_reset.75901340851329716862360371616789423313854271094339983437889482112063859396899
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4269625378 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 4269625378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.61688220102430516602736759087215106568065278898160443360524010209369264708576
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 358605278 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 358605278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.83415664626448639459551650003611915154093605658125839275503566895709283694298
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @ 5590243650 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 1134691281 [0x43a203d1])
  UVM_INFO @ 5590243650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.96876177074295677306688860665444995041103847648909643373435305373674558344655
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 654718733 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 654718733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 4.rv_dm_stress_all.94980795633038781379208697080719329311465384632653035657410540005227749692433
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 9509227134 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x6e408100)
  UVM_INFO @ 9509227134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.2429896636446945823930891145755603910500926323532881389175641853670183068889
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 636230486 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 636230486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.35144691194949919790328206903168492723149536325976493427178732967061436033692
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3451063161 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1978071554 [0x75e6fa02]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 3451063161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:51) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 18.rv_dm_stress_all.106270759612549476382850872531838105515858714549657339914491835191334352611354
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 20645348559 ps: (rv_dm_ndmreset_req_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
  UVM_INFO @ 20645348559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 33.rv_dm_stress_all.39842956589370400250390714612102666916269004411760536499290185894050963850012
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 17113986479 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 17113986479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```