Line Coverage for Module :
dmi_jtag
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 88 | 83 | 94.32 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| ALWAYS | 72 | 7 | 7 | 100.00 |
| ALWAYS | 94 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| ALWAYS | 141 | 49 | 44 | 89.80 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 263 | 12 | 12 | 100.00 |
| ALWAYS | 287 | 11 | 11 | 100.00 |
64
65 1/1 assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
Tests: T1 T2 T3
66
67 // -------------------------------
68 // Debug Module Control and Status
69 // -------------------------------
70
71 always_comb begin
72 1/1 dtmcs_d = dtmcs_q;
Tests: T1 T2 T3
73 1/1 if (capture) begin
Tests: T1 T2 T3
74 1/1 if (dtmcs_select) begin
Tests: T1 T2 T3
75 1/1 dtmcs_d = '{
Tests: T1 T2 T3
76 zero1 : '0,
77 dmihardreset : 1'b0,
78 dmireset : 1'b0,
79 zero0 : '0,
80 idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
81 dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast
82 abits : 6'(NumDmiWordAbits), // The size of address in dmi
83 version : 4'd1 // Version described in spec version 0.13 (and later?)
84 };
85 end
MISSING_ELSE
86 end
MISSING_ELSE
87
88 1/1 if (shift) begin
Tests: T1 T2 T3
89 2/2 if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)};
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
90 end
MISSING_ELSE
91 end
92
93 always_ff @(posedge tck or negedge trst_ni) begin
94 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
95 1/1 dtmcs_q <= '0;
Tests: T1 T2 T3
96 end else begin
97 1/1 dtmcs_q <= dtmcs_d;
Tests: T1 T2 T3
98 end
99 end
100
101 // ----------------------------
102 // DMI (Debug Module Interface)
103 // ----------------------------
104
105 logic dmi_select;
106 logic dmi_tdo;
107
108 dm::dmi_req_t dmi_req;
109 logic dmi_req_ready;
110 logic dmi_req_valid;
111
112 dm::dmi_resp_t dmi_resp;
113 logic dmi_resp_valid;
114 logic dmi_resp_ready;
115
116 typedef struct packed {
117 logic [NumDmiWordAbits-1:0] address;
118 logic [31:0] data;
119 logic [1:0] op;
120 } dmi_t;
121
122 typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e;
123 state_e state_d, state_q;
124
125 logic [$bits(dmi_t)-1:0] dr_d, dr_q;
126 logic [NumDmiWordAbits-1:0] address_d, address_q;
127 logic [31:0] data_d, data_q;
128
129 dmi_t dmi;
130 1/1 assign dmi = dmi_t'(dr_q);
Tests: T1 T2 T3
131 1/1 assign dmi_req.addr = $bits(dmi_req.addr)'(address_q);
Tests: T1 T2 T3
132 1/1 assign dmi_req.data = data_q;
Tests: T1 T2 T3
133 1/1 assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
Tests: T1 T2 T3
134 // We will always be ready to accept the data we requested.
135 assign dmi_resp_ready = 1'b1;
136
137 logic error_dmi_busy;
138 logic error_dmi_op_failed;
139
140 always_comb begin : p_fsm
141 1/1 error_dmi_busy = 1'b0;
Tests: T1 T2 T3
142 1/1 error_dmi_op_failed = 1'b0;
Tests: T1 T2 T3
143 // default assignments
144 1/1 state_d = state_q;
Tests: T1 T2 T3
145 1/1 address_d = address_q;
Tests: T1 T2 T3
146 1/1 data_d = data_q;
Tests: T1 T2 T3
147 1/1 error_d = error_q;
Tests: T1 T2 T3
148
149 1/1 dmi_req_valid = 1'b0;
Tests: T1 T2 T3
150
151 1/1 if (dmi_clear) begin
Tests: T1 T2 T3
152 1/1 state_d = Idle;
Tests: T1 T2 T3
153 1/1 data_d = '0;
Tests: T1 T2 T3
154 1/1 error_d = DMINoError;
Tests: T1 T2 T3
155 1/1 address_d = '0;
Tests: T1 T2 T3
156 end else begin
157 1/1 unique case (state_q)
Tests: T1 T2 T3
158 Idle: begin
159 // make sure that no error is sticky
160 1/1 if (dmi_select && update && (error_q == DMINoError)) begin
Tests: T1 T2 T3
161 // save address and value
162 1/1 address_d = dmi.address;
Tests: T1 T2 T3
163 1/1 data_d = dmi.data;
Tests: T1 T2 T3
164 1/1 if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
Tests: T1 T2 T3
165 1/1 state_d = Read;
Tests: T1 T2 T3
166 1/1 end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
Tests: T1 T2 T3
167 1/1 state_d = Write;
Tests: T1 T2 T3
168 end
MISSING_ELSE
169 // else this is a nop and we can stay here
170 end
MISSING_ELSE
171 end
172
173 Read: begin
174 1/1 dmi_req_valid = 1'b1;
Tests: T1 T2 T3
175 1/1 if (dmi_req_ready) begin
Tests: T1 T2 T3
176 1/1 state_d = WaitReadValid;
Tests: T1 T2 T3
177 end
==> MISSING_ELSE
178 end
179
180 WaitReadValid: begin
181 // load data into register and shift out
182 1/1 if (dmi_resp_valid) begin
Tests: T1 T2 T3
183 1/1 unique case (dmi_resp.resp)
Tests: T1 T2 T3
184 dm::DTM_SUCCESS: begin
185 1/1 data_d = dmi_resp.data;
Tests: T1 T2 T3
186 end
187 dm::DTM_ERR: begin
188 0/1 ==> data_d = 32'hDEAD_BEEF;
189 0/1 ==> error_dmi_op_failed = 1'b1;
190 end
191 dm::DTM_BUSY: begin
192 1/1 data_d = 32'hB051_B051;
Tests: T9 T10 T11
193 1/1 error_dmi_busy = 1'b1;
Tests: T9 T10 T11
194 end
195 default: begin
196 data_d = 32'hBAAD_C0DE;
197 end
198 endcase
199 1/1 state_d = Idle;
Tests: T1 T2 T3
200 end
MISSING_ELSE
201 end
202
203 Write: begin
204 1/1 dmi_req_valid = 1'b1;
Tests: T1 T2 T3
205 // request sent, wait for response before going back to idle
206 1/1 if (dmi_req_ready) begin
Tests: T1 T2 T3
207 1/1 state_d = WaitWriteValid;
Tests: T1 T2 T3
208 end
==> MISSING_ELSE
209 end
210
211 WaitWriteValid: begin
212 // got a valid answer go back to idle
213 1/1 if (dmi_resp_valid) begin
Tests: T1 T2 T3
214 1/1 unique case (dmi_resp.resp)
Tests: T1 T2 T3
215 0/1 ==> dm::DTM_ERR: error_dmi_op_failed = 1'b1;
216 1/1 dm::DTM_BUSY: error_dmi_busy = 1'b1;
Tests: T3 T28 T29
217 default: ;
218 endcase
219 1/1 state_d = Idle;
Tests: T1 T2 T3
220 end
MISSING_ELSE
221 end
222
223 default: begin
224 // just wait for idle here
225 if (dmi_resp_valid) begin
226 state_d = Idle;
227 end
MISSING_ELSE
228 end
229 endcase
230
231 // update means we got another request but we didn't finish
232 // the one in progress, this state is sticky
233 1/1 if (update && state_q != Idle) begin
Tests: T1 T2 T3
234 0/1 ==> error_dmi_busy = 1'b1;
235 end
MISSING_ELSE
236
237 // if capture goes high while we are in the read state
238 // or in the corresponding wait state we are not giving back a valid word
239 // -> throw an error
240 1/1 if (capture && state_q inside {Read, WaitReadValid}) begin
Tests: T1 T2 T3
241 1/1 error_dmi_busy = 1'b1;
Tests: T8 T74 T75
242 end
MISSING_ELSE
243
244 1/1 if (error_dmi_busy && error_q == DMINoError) begin
Tests: T1 T2 T3
245 1/1 error_d = DMIBusy;
Tests: T3 T28 T8
246 end
MISSING_ELSE
247
248 1/1 if (error_dmi_op_failed && error_q == DMINoError) begin
Tests: T1 T2 T3
249 0/1 ==> error_d = DMIOPFailed;
250 end
MISSING_ELSE
251
252 // clear sticky error flag
253 1/1 if (update && dtmcs_q.dmireset && dtmcs_select) begin
Tests: T1 T2 T3
254 1/1 error_d = DMINoError;
Tests: T3 T28 T8
255 end
MISSING_ELSE
256 end
257 end
258
259 // shift register
260 1/1 assign dmi_tdo = dr_q[0];
Tests: T1 T2 T3
261
262 always_comb begin : p_shift
263 1/1 dr_d = dr_q;
Tests: T1 T2 T3
264 1/1 if (dmi_clear) begin
Tests: T1 T2 T3
265 1/1 dr_d = '0;
Tests: T1 T2 T3
266 end else begin
267 1/1 if (capture) begin
Tests: T1 T2 T3
268 1/1 if (dmi_select) begin
Tests: T1 T2 T3
269 1/1 if (error_q == DMINoError && !error_dmi_busy) begin
Tests: T1 T2 T3
270 1/1 dr_d = {address_q, data_q, DMINoError};
Tests: T1 T2 T3
271 // DMI was busy, report an error
272 1/1 end else if (error_q == DMIBusy || error_dmi_busy) begin
Tests: T1 T2 T3
273 1/1 dr_d = {address_q, data_q, DMIBusy};
Tests: T1 T2 T3
274 end
MISSING_ELSE
275 end
MISSING_ELSE
276 end
MISSING_ELSE
277
278 1/1 if (shift) begin
Tests: T1 T2 T3
279 1/1 if (dmi_select) begin
Tests: T1 T2 T3
280 1/1 dr_d = {tdi, dr_q[$bits(dr_q)-1:1]};
Tests: T1 T2 T3
281 end
MISSING_ELSE
282 end
MISSING_ELSE
283 end
284 end
285
286 always_ff @(posedge tck or negedge trst_ni) begin
287 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
288 1/1 dr_q <= '0;
Tests: T1 T2 T3
289 1/1 state_q <= Idle;
Tests: T1 T2 T3
290 1/1 address_q <= '0;
Tests: T1 T2 T3
291 1/1 data_q <= '0;
Tests: T1 T2 T3
292 1/1 error_q <= DMINoError;
Tests: T1 T2 T3
293 end else begin
294 1/1 dr_q <= dr_d;
Tests: T1 T2 T3
295 1/1 state_q <= state_d;
Tests: T1 T2 T3
296 1/1 address_q <= address_d;
Tests: T1 T2 T3
297 1/1 data_q <= data_d;
Tests: T1 T2 T3
298 1/1 error_q <= error_d;
Tests: T1 T2 T3
Cond Coverage for Module :
dmi_jtag
| Total | Covered | Percent |
|---|
| Conditions | 53 | 48 | 90.57 |
| Logical | 53 | 48 | 90.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 65
EXPRESSION (jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset))
-------1------ ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T76,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 65
SUB-EXPRESSION (dtmcs_select && update && dtmcs_q.dmihardreset)
------1----- ---2-- ----------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T7,T76,T27 |
| 1 | 0 | 1 | Covered | T3,T23,T7 |
| 1 | 1 | 0 | Covered | T3,T23,T28 |
| 1 | 1 | 1 | Covered | T7,T76,T27 |
LINE 133
EXPRESSION ((state_q == Write) ? DTM_WRITE : DTM_READ)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 133
SUB-EXPRESSION (state_q == Write)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (dmi_select && update && (error_q == DMINoError))
-----1---- ---2-- -----------3-----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T23,T77,T8 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T3,T28,T8 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (dtm_op_e'(dmi.op) == DTM_READ)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (dtm_op_e'(dmi.op) == DTM_WRITE)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 233
EXPRESSION (update && (state_q != Idle))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Not Covered | |
LINE 233
SUB-EXPRESSION (state_q != Idle)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 240
EXPRESSION (capture && (state_q inside {Read, WaitReadValid}))
---1--- -------------------2------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T8,T74,T75 |
LINE 244
EXPRESSION (error_dmi_busy && (error_q == DMINoError))
-------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T28,T8 |
LINE 244
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 248
EXPRESSION (error_dmi_op_failed && (error_q == DMINoError))
---------1--------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 248
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 253
EXPRESSION (update && dtmcs_q.dmireset && dtmcs_select)
---1-- --------2------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T3,T23,T7 |
| 1 | 0 | 1 | Covered | T23,T8,T78 |
| 1 | 1 | 0 | Covered | T3,T28,T8 |
| 1 | 1 | 1 | Covered | T3,T28,T8 |
LINE 269
EXPRESSION ((error_q == DMINoError) && ((!error_dmi_busy)))
-----------1----------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T28,T29 |
| 1 | 0 | Covered | T8,T74,T75 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 269
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 272
EXPRESSION ((error_q == DMIBusy) || error_dmi_busy)
----------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T8,T74,T75 |
| 1 | 0 | Covered | T3,T28,T29 |
LINE 272
SUB-EXPRESSION (error_q == DMIBusy)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
FSM Coverage for Module :
dmi_jtag
Summary for FSM :: error_q
| Total | Covered | Percent | |
| States |
3 |
2 |
66.67 |
(Not included in score) |
| Transitions |
4 |
2 |
50.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
| states | Line No. | Covered | Tests |
| DMIBusy |
245 |
Covered |
T3,T28,T8 |
| DMINoError |
292 |
Covered |
T1,T2,T3 |
| DMIOPFailed |
249 |
Not Covered |
|
| transitions | Line No. | Covered | Tests |
| DMIBusy->DMINoError |
292 |
Covered |
T3,T28,T8 |
| DMINoError->DMIBusy |
245 |
Covered |
T3,T28,T8 |
| DMINoError->DMIOPFailed |
249 |
Not Covered |
|
| DMIOPFailed->DMINoError |
292 |
Not Covered |
|
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
8 |
8 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| Idle |
289 |
Covered |
T1,T2,T3 |
| Read |
165 |
Covered |
T1,T2,T3 |
| WaitReadValid |
176 |
Covered |
T1,T2,T3 |
| WaitWriteValid |
207 |
Covered |
T1,T2,T3 |
| Write |
167 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| Idle->Read |
165 |
Covered |
T1,T2,T3 |
| Idle->Write |
167 |
Covered |
T1,T2,T3 |
| Read->Idle |
289 |
Covered |
T74,T79 |
| Read->WaitReadValid |
176 |
Covered |
T1,T2,T3 |
| WaitReadValid->Idle |
289 |
Covered |
T1,T2,T3 |
| WaitWriteValid->Idle |
289 |
Covered |
T1,T2,T3 |
| Write->Idle |
289 |
Covered |
T8 |
| Write->WaitWriteValid |
207 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
dmi_jtag
| Line No. | Total | Covered | Percent |
| Branches |
|
51 |
42 |
82.35 |
| TERNARY |
133 |
2 |
2 |
100.00 |
| IF |
73 |
3 |
3 |
100.00 |
| IF |
88 |
3 |
3 |
100.00 |
| IF |
94 |
2 |
2 |
100.00 |
| IF |
151 |
30 |
21 |
70.00 |
| IF |
264 |
9 |
9 |
100.00 |
| IF |
287 |
2 |
2 |
100.00 |
133 assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
73 if (capture) begin
-1-
74 if (dtmcs_select) begin
-2-
75 dtmcs_d = '{
==>
76 zero1 : '0,
77 dmihardreset : 1'b0,
78 dmireset : 1'b0,
79 zero0 : '0,
80 idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
81 dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast
82 abits : 6'(NumDmiWordAbits), // The size of address in dmi
83 version : 4'd1 // Version described in spec version 0.13 (and later?)
84 };
85 end
MISSING_ELSE
==>
86 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
88 if (shift) begin
-1-
89 if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)};
-2-
==>
MISSING_ELSE
==>
90 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
94 if (!trst_ni) begin
-1-
95 dtmcs_q <= '0;
==>
96 end else begin
97 dtmcs_q <= dtmcs_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
151 if (dmi_clear) begin
-1-
152 state_d = Idle;
==>
153 data_d = '0;
154 error_d = DMINoError;
155 address_d = '0;
156 end else begin
157 unique case (state_q)
-2-
158 Idle: begin
159 // make sure that no error is sticky
160 if (dmi_select && update && (error_q == DMINoError)) begin
-3-
161 // save address and value
162 address_d = dmi.address;
163 data_d = dmi.data;
164 if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
-4-
165 state_d = Read;
==>
166 end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
-5-
167 state_d = Write;
==>
168 end
MISSING_ELSE
==>
169 // else this is a nop and we can stay here
170 end
MISSING_ELSE
==>
171 end
172
173 Read: begin
174 dmi_req_valid = 1'b1;
175 if (dmi_req_ready) begin
-6-
176 state_d = WaitReadValid;
==>
177 end
MISSING_ELSE
==>
178 end
179
180 WaitReadValid: begin
181 // load data into register and shift out
182 if (dmi_resp_valid) begin
-7-
183 unique case (dmi_resp.resp)
-8-
184 dm::DTM_SUCCESS: begin
185 data_d = dmi_resp.data;
==>
186 end
187 dm::DTM_ERR: begin
188 data_d = 32'hDEAD_BEEF;
==>
189 error_dmi_op_failed = 1'b1;
190 end
191 dm::DTM_BUSY: begin
192 data_d = 32'hB051_B051;
==>
193 error_dmi_busy = 1'b1;
194 end
195 default: begin
196 data_d = 32'hBAAD_C0DE;
==>
197 end
198 endcase
199 state_d = Idle;
200 end
MISSING_ELSE
==>
201 end
202
203 Write: begin
204 dmi_req_valid = 1'b1;
205 // request sent, wait for response before going back to idle
206 if (dmi_req_ready) begin
-9-
207 state_d = WaitWriteValid;
==>
208 end
MISSING_ELSE
==>
209 end
210
211 WaitWriteValid: begin
212 // got a valid answer go back to idle
213 if (dmi_resp_valid) begin
-10-
214 unique case (dmi_resp.resp)
-11-
215 dm::DTM_ERR: error_dmi_op_failed = 1'b1;
==>
216 dm::DTM_BUSY: error_dmi_busy = 1'b1;
==>
217 default: ;
==>
218 endcase
219 state_d = Idle;
220 end
MISSING_ELSE
==>
221 end
222
223 default: begin
224 // just wait for idle here
225 if (dmi_resp_valid) begin
-12-
226 state_d = Idle;
==>
227 end
MISSING_ELSE
==>
228 end
229 endcase
230
231 // update means we got another request but we didn't finish
232 // the one in progress, this state is sticky
233 if (update && state_q != Idle) begin
-13-
234 error_dmi_busy = 1'b1;
==>
235 end
MISSING_ELSE
==>
236
237 // if capture goes high while we are in the read state
238 // or in the corresponding wait state we are not giving back a valid word
239 // -> throw an error
240 if (capture && state_q inside {Read, WaitReadValid}) begin
-14-
241 error_dmi_busy = 1'b1;
==>
242 end
MISSING_ELSE
==>
243
244 if (error_dmi_busy && error_q == DMINoError) begin
-15-
245 error_d = DMIBusy;
==>
246 end
MISSING_ELSE
==>
247
248 if (error_dmi_op_failed && error_q == DMINoError) begin
-16-
249 error_d = DMIOPFailed;
==>
250 end
MISSING_ELSE
==>
251
252 // clear sticky error flag
253 if (update && dtmcs_q.dmireset && dtmcs_select) begin
-17-
254 error_d = DMINoError;
==>
255 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Read |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Read |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_SUCCESS |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_ERR |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_BUSY |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T10,T11 |
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Write |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Write |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
DTM_ERR |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
DTM_BUSY |
- |
- |
- |
- |
- |
- |
Covered |
T3,T28,T29 |
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T8,T74,T75 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T3,T28,T8 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T28,T8 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
264 if (dmi_clear) begin
-1-
265 dr_d = '0;
==>
266 end else begin
267 if (capture) begin
-2-
268 if (dmi_select) begin
-3-
269 if (error_q == DMINoError && !error_dmi_busy) begin
-4-
270 dr_d = {address_q, data_q, DMINoError};
==>
271 // DMI was busy, report an error
272 end else if (error_q == DMIBusy || error_dmi_busy) begin
-5-
273 dr_d = {address_q, data_q, DMIBusy};
==>
274 end
MISSING_ELSE
==>
275 end
MISSING_ELSE
==>
276 end
MISSING_ELSE
==>
277
278 if (shift) begin
-6-
279 if (dmi_select) begin
-7-
280 dr_d = {tdi, dr_q[$bits(dr_q)-1:1]};
==>
281 end
MISSING_ELSE
==>
282 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
287 if (!trst_ni) begin
-1-
288 dr_q <= '0;
==>
289 state_q <= Idle;
290 address_q <= '0;
291 data_q <= '0;
292 error_q <= DMINoError;
293 end else begin
294 dr_q <= dr_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.dap
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 84 | 83 | 98.81 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| ALWAYS | 72 | 7 | 7 | 100.00 |
| ALWAYS | 94 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| ALWAYS | 141 | 45 | 44 | 97.78 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 263 | 12 | 12 | 100.00 |
| ALWAYS | 287 | 11 | 11 | 100.00 |
64
65 1/1 assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
Tests: T1 T2 T3
66
67 // -------------------------------
68 // Debug Module Control and Status
69 // -------------------------------
70
71 always_comb begin
72 1/1 dtmcs_d = dtmcs_q;
Tests: T1 T2 T3
73 1/1 if (capture) begin
Tests: T1 T2 T3
74 1/1 if (dtmcs_select) begin
Tests: T1 T2 T3
75 1/1 dtmcs_d = '{
Tests: T1 T2 T3
76 zero1 : '0,
77 dmihardreset : 1'b0,
78 dmireset : 1'b0,
79 zero0 : '0,
80 idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
81 dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast
82 abits : 6'(NumDmiWordAbits), // The size of address in dmi
83 version : 4'd1 // Version described in spec version 0.13 (and later?)
84 };
85 end
MISSING_ELSE
86 end
MISSING_ELSE
87
88 1/1 if (shift) begin
Tests: T1 T2 T3
89 2/2 if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)};
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
90 end
MISSING_ELSE
91 end
92
93 always_ff @(posedge tck or negedge trst_ni) begin
94 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
95 1/1 dtmcs_q <= '0;
Tests: T1 T2 T3
96 end else begin
97 1/1 dtmcs_q <= dtmcs_d;
Tests: T1 T2 T3
98 end
99 end
100
101 // ----------------------------
102 // DMI (Debug Module Interface)
103 // ----------------------------
104
105 logic dmi_select;
106 logic dmi_tdo;
107
108 dm::dmi_req_t dmi_req;
109 logic dmi_req_ready;
110 logic dmi_req_valid;
111
112 dm::dmi_resp_t dmi_resp;
113 logic dmi_resp_valid;
114 logic dmi_resp_ready;
115
116 typedef struct packed {
117 logic [NumDmiWordAbits-1:0] address;
118 logic [31:0] data;
119 logic [1:0] op;
120 } dmi_t;
121
122 typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e;
123 state_e state_d, state_q;
124
125 logic [$bits(dmi_t)-1:0] dr_d, dr_q;
126 logic [NumDmiWordAbits-1:0] address_d, address_q;
127 logic [31:0] data_d, data_q;
128
129 dmi_t dmi;
130 1/1 assign dmi = dmi_t'(dr_q);
Tests: T1 T2 T3
131 1/1 assign dmi_req.addr = $bits(dmi_req.addr)'(address_q);
Tests: T1 T2 T3
132 1/1 assign dmi_req.data = data_q;
Tests: T1 T2 T3
133 1/1 assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
Tests: T1 T2 T3
134 // We will always be ready to accept the data we requested.
135 assign dmi_resp_ready = 1'b1;
136
137 logic error_dmi_busy;
138 logic error_dmi_op_failed;
139
140 always_comb begin : p_fsm
141 1/1 error_dmi_busy = 1'b0;
Tests: T1 T2 T3
142 1/1 error_dmi_op_failed = 1'b0;
Tests: T1 T2 T3
143 // default assignments
144 1/1 state_d = state_q;
Tests: T1 T2 T3
145 1/1 address_d = address_q;
Tests: T1 T2 T3
146 1/1 data_d = data_q;
Tests: T1 T2 T3
147 1/1 error_d = error_q;
Tests: T1 T2 T3
148
149 1/1 dmi_req_valid = 1'b0;
Tests: T1 T2 T3
150
151 1/1 if (dmi_clear) begin
Tests: T1 T2 T3
152 1/1 state_d = Idle;
Tests: T1 T2 T3
153 1/1 data_d = '0;
Tests: T1 T2 T3
154 1/1 error_d = DMINoError;
Tests: T1 T2 T3
155 1/1 address_d = '0;
Tests: T1 T2 T3
156 end else begin
157 1/1 unique case (state_q)
Tests: T1 T2 T3
158 Idle: begin
159 // make sure that no error is sticky
160 1/1 if (dmi_select && update && (error_q == DMINoError)) begin
Tests: T1 T2 T3
161 // save address and value
162 1/1 address_d = dmi.address;
Tests: T1 T2 T3
163 1/1 data_d = dmi.data;
Tests: T1 T2 T3
164 1/1 if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
Tests: T1 T2 T3
165 1/1 state_d = Read;
Tests: T1 T2 T3
166 1/1 end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
Tests: T1 T2 T3
167 1/1 state_d = Write;
Tests: T1 T2 T3
168 end
MISSING_ELSE
169 // else this is a nop and we can stay here
170 end
MISSING_ELSE
171 end
172
173 Read: begin
174 1/1 dmi_req_valid = 1'b1;
Tests: T1 T2 T3
175 1/1 if (dmi_req_ready) begin
Tests: T1 T2 T3
176 1/1 state_d = WaitReadValid;
Tests: T1 T2 T3
177 end
==> MISSING_ELSE
178 end
179
180 WaitReadValid: begin
181 // load data into register and shift out
182 1/1 if (dmi_resp_valid) begin
Tests: T1 T2 T3
183 1/1 unique case (dmi_resp.resp)
Tests: T1 T2 T3
184 dm::DTM_SUCCESS: begin
185 1/1 data_d = dmi_resp.data;
Tests: T1 T2 T3
186 end
187 dm::DTM_ERR: begin
188 excluded data_d = 32'hDEAD_BEEF;
Exclude Annotation: dmi_jtag.sv, line 188: dm_top cannot respond with DTM_ERR
189 excluded error_dmi_op_failed = 1'b1;
Exclude Annotation: dmi_jtag.sv, line 188: dm_top cannot respond with DTM_ERR
190 end
191 dm::DTM_BUSY: begin
192 1/1 data_d = 32'hB051_B051;
Tests: T9 T10 T11
193 1/1 error_dmi_busy = 1'b1;
Tests: T9 T10 T11
194 end
195 default: begin
196 data_d = 32'hBAAD_C0DE;
197 end
198 endcase
199 1/1 state_d = Idle;
Tests: T1 T2 T3
200 end
MISSING_ELSE
201 end
202
203 Write: begin
204 1/1 dmi_req_valid = 1'b1;
Tests: T1 T2 T3
205 // request sent, wait for response before going back to idle
206 1/1 if (dmi_req_ready) begin
Tests: T1 T2 T3
207 1/1 state_d = WaitWriteValid;
Tests: T1 T2 T3
208 end
==> MISSING_ELSE
209 end
210
211 WaitWriteValid: begin
212 // got a valid answer go back to idle
213 1/1 if (dmi_resp_valid) begin
Tests: T1 T2 T3
214 1/1 unique case (dmi_resp.resp)
Tests: T1 T2 T3
215 excluded dm::DTM_ERR: error_dmi_op_failed = 1'b1;
Exclude Annotation: dmi_jtag.sv, line 215: dm_top cannot respond with DTM_ERR
216 1/1 dm::DTM_BUSY: error_dmi_busy = 1'b1;
Tests: T3 T28 T29
217 default: ;
218 endcase
219 1/1 state_d = Idle;
Tests: T1 T2 T3
220 end
MISSING_ELSE
221 end
222
223 default: begin
224 // just wait for idle here
225 if (dmi_resp_valid) begin
226 state_d = Idle;
227 end
MISSING_ELSE
228 end
229 endcase
230
231 // update means we got another request but we didn't finish
232 // the one in progress, this state is sticky
233 1/1 if (update && state_q != Idle) begin
Tests: T1 T2 T3
234 0/1 ==> error_dmi_busy = 1'b1;
235 end
MISSING_ELSE
236
237 // if capture goes high while we are in the read state
238 // or in the corresponding wait state we are not giving back a valid word
239 // -> throw an error
240 1/1 if (capture && state_q inside {Read, WaitReadValid}) begin
Tests: T1 T2 T3
241 1/1 error_dmi_busy = 1'b1;
Tests: T8 T74 T75
242 end
MISSING_ELSE
243
244 1/1 if (error_dmi_busy && error_q == DMINoError) begin
Tests: T1 T2 T3
245 1/1 error_d = DMIBusy;
Tests: T3 T28 T8
246 end
MISSING_ELSE
247
248 1/1 if (error_dmi_op_failed && error_q == DMINoError) begin
Tests: T1 T2 T3
249 excluded error_d = DMIOPFailed;
Exclude Annotation: dmi_jtag.sv, line 215: dm_top cannot respond with DTM_ERR (needed for error_dmi_op_failed)
250 end
MISSING_ELSE
251
252 // clear sticky error flag
253 1/1 if (update && dtmcs_q.dmireset && dtmcs_select) begin
Tests: T1 T2 T3
254 1/1 error_d = DMINoError;
Tests: T3 T28 T8
255 end
MISSING_ELSE
256 end
257 end
258
259 // shift register
260 1/1 assign dmi_tdo = dr_q[0];
Tests: T1 T2 T3
261
262 always_comb begin : p_shift
263 1/1 dr_d = dr_q;
Tests: T1 T2 T3
264 1/1 if (dmi_clear) begin
Tests: T1 T2 T3
265 1/1 dr_d = '0;
Tests: T1 T2 T3
266 end else begin
267 1/1 if (capture) begin
Tests: T1 T2 T3
268 1/1 if (dmi_select) begin
Tests: T1 T2 T3
269 1/1 if (error_q == DMINoError && !error_dmi_busy) begin
Tests: T1 T2 T3
270 1/1 dr_d = {address_q, data_q, DMINoError};
Tests: T1 T2 T3
271 // DMI was busy, report an error
272 1/1 end else if (error_q == DMIBusy || error_dmi_busy) begin
Tests: T1 T2 T3
273 1/1 dr_d = {address_q, data_q, DMIBusy};
Tests: T1 T2 T3
274 end
MISSING_ELSE
275 end
MISSING_ELSE
276 end
MISSING_ELSE
277
278 1/1 if (shift) begin
Tests: T1 T2 T3
279 1/1 if (dmi_select) begin
Tests: T1 T2 T3
280 1/1 dr_d = {tdi, dr_q[$bits(dr_q)-1:1]};
Tests: T1 T2 T3
281 end
MISSING_ELSE
282 end
MISSING_ELSE
283 end
284 end
285
286 always_ff @(posedge tck or negedge trst_ni) begin
287 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
288 1/1 dr_q <= '0;
Tests: T1 T2 T3
289 1/1 state_q <= Idle;
Tests: T1 T2 T3
290 1/1 address_q <= '0;
Tests: T1 T2 T3
291 1/1 data_q <= '0;
Tests: T1 T2 T3
292 1/1 error_q <= DMINoError;
Tests: T1 T2 T3
293 end else begin
294 1/1 dr_q <= dr_d;
Tests: T1 T2 T3
295 1/1 state_q <= state_d;
Tests: T1 T2 T3
296 1/1 address_q <= address_d;
Tests: T1 T2 T3
297 1/1 data_q <= data_d;
Tests: T1 T2 T3
298 1/1 error_q <= error_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.dap
| Total | Covered | Percent |
|---|
| Conditions | 53 | 48 | 90.57 |
| Logical | 53 | 48 | 90.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 65
EXPRESSION (jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset))
-------1------ ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T76,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 65
SUB-EXPRESSION (dtmcs_select && update && dtmcs_q.dmihardreset)
------1----- ---2-- ----------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T7,T76,T27 |
| 1 | 0 | 1 | Covered | T3,T23,T7 |
| 1 | 1 | 0 | Covered | T3,T23,T28 |
| 1 | 1 | 1 | Covered | T7,T76,T27 |
LINE 133
EXPRESSION ((state_q == Write) ? DTM_WRITE : DTM_READ)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 133
SUB-EXPRESSION (state_q == Write)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (dmi_select && update && (error_q == DMINoError))
-----1---- ---2-- -----------3-----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T23,T77,T8 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T3,T28,T8 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (dtm_op_e'(dmi.op) == DTM_READ)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (dtm_op_e'(dmi.op) == DTM_WRITE)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 233
EXPRESSION (update && (state_q != Idle))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Not Covered | |
LINE 233
SUB-EXPRESSION (state_q != Idle)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 240
EXPRESSION (capture && (state_q inside {Read, WaitReadValid}))
---1--- -------------------2------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T8,T74,T75 |
LINE 244
EXPRESSION (error_dmi_busy && (error_q == DMINoError))
-------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T28,T8 |
LINE 244
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 248
EXPRESSION (error_dmi_op_failed && (error_q == DMINoError))
---------1--------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 248
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T28,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 253
EXPRESSION (update && dtmcs_q.dmireset && dtmcs_select)
---1-- --------2------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T3,T23,T7 |
| 1 | 0 | 1 | Covered | T23,T8,T78 |
| 1 | 1 | 0 | Covered | T3,T28,T8 |
| 1 | 1 | 1 | Covered | T3,T28,T8 |
LINE 269
EXPRESSION ((error_q == DMINoError) && ((!error_dmi_busy)))
-----------1----------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T28,T29 |
| 1 | 0 | Covered | T8,T74,T75 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 269
SUB-EXPRESSION (error_q == DMINoError)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 272
EXPRESSION ((error_q == DMIBusy) || error_dmi_busy)
----------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T8,T74,T75 |
| 1 | 0 | Covered | T3,T28,T29 |
LINE 272
SUB-EXPRESSION (error_q == DMIBusy)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
FSM Coverage for Instance : tb.dut.dap
Summary for FSM :: error_q
| Total | Covered | Percent | |
| States |
2 |
2 |
100.00 |
(Not included in score) |
| Transitions |
2 |
2 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
| states | Line No. | Covered | Tests |
| DMIBusy |
245 |
Covered |
T3,T28,T8 |
| DMINoError |
292 |
Covered |
T1,T2,T3 |
| DMIOPFailed |
249 |
Excluded |
|
| transitions | Line No. | Covered | Tests |
| DMIBusy->DMINoError |
292 |
Covered |
T3,T28,T8 |
| DMINoError->DMIBusy |
245 |
Covered |
T3,T28,T8 |
| DMINoError->DMIOPFailed |
249 |
Excluded |
|
| DMIOPFailed->DMINoError |
292 |
Excluded |
|
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
8 |
8 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| Idle |
289 |
Covered |
T1,T2,T3 |
| Read |
165 |
Covered |
T1,T2,T3 |
| WaitReadValid |
176 |
Covered |
T1,T2,T3 |
| WaitWriteValid |
207 |
Covered |
T1,T2,T3 |
| Write |
167 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| Idle->Read |
165 |
Covered |
T1,T2,T3 |
| Idle->Write |
167 |
Covered |
T1,T2,T3 |
| Read->Idle |
289 |
Covered |
T74,T79 |
| Read->WaitReadValid |
176 |
Covered |
T1,T2,T3 |
| WaitReadValid->Idle |
289 |
Covered |
T1,T2,T3 |
| WaitWriteValid->Idle |
289 |
Covered |
T1,T2,T3 |
| Write->Idle |
289 |
Covered |
T8 |
| Write->WaitWriteValid |
207 |
Covered |
T1,T2,T3 |
Branch Coverage for Instance : tb.dut.dap
| Line No. | Total | Covered | Percent |
| Branches |
|
51 |
42 |
82.35 |
| TERNARY |
133 |
2 |
2 |
100.00 |
| IF |
73 |
3 |
3 |
100.00 |
| IF |
88 |
3 |
3 |
100.00 |
| IF |
94 |
2 |
2 |
100.00 |
| IF |
151 |
30 |
21 |
70.00 |
| IF |
264 |
9 |
9 |
100.00 |
| IF |
287 |
2 |
2 |
100.00 |
133 assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
73 if (capture) begin
-1-
74 if (dtmcs_select) begin
-2-
75 dtmcs_d = '{
==>
76 zero1 : '0,
77 dmihardreset : 1'b0,
78 dmireset : 1'b0,
79 zero0 : '0,
80 idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
81 dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast
82 abits : 6'(NumDmiWordAbits), // The size of address in dmi
83 version : 4'd1 // Version described in spec version 0.13 (and later?)
84 };
85 end
MISSING_ELSE
==>
86 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
88 if (shift) begin
-1-
89 if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)};
-2-
==>
MISSING_ELSE
==>
90 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
94 if (!trst_ni) begin
-1-
95 dtmcs_q <= '0;
==>
96 end else begin
97 dtmcs_q <= dtmcs_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
151 if (dmi_clear) begin
-1-
152 state_d = Idle;
==>
153 data_d = '0;
154 error_d = DMINoError;
155 address_d = '0;
156 end else begin
157 unique case (state_q)
-2-
158 Idle: begin
159 // make sure that no error is sticky
160 if (dmi_select && update && (error_q == DMINoError)) begin
-3-
161 // save address and value
162 address_d = dmi.address;
163 data_d = dmi.data;
164 if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
-4-
165 state_d = Read;
==>
166 end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
-5-
167 state_d = Write;
==>
168 end
MISSING_ELSE
==>
169 // else this is a nop and we can stay here
170 end
MISSING_ELSE
==>
171 end
172
173 Read: begin
174 dmi_req_valid = 1'b1;
175 if (dmi_req_ready) begin
-6-
176 state_d = WaitReadValid;
==>
177 end
MISSING_ELSE
==>
178 end
179
180 WaitReadValid: begin
181 // load data into register and shift out
182 if (dmi_resp_valid) begin
-7-
183 unique case (dmi_resp.resp)
-8-
184 dm::DTM_SUCCESS: begin
185 data_d = dmi_resp.data;
==>
186 end
187 dm::DTM_ERR: begin
188 data_d = 32'hDEAD_BEEF;
==>
189 error_dmi_op_failed = 1'b1;
190 end
191 dm::DTM_BUSY: begin
192 data_d = 32'hB051_B051;
==>
193 error_dmi_busy = 1'b1;
194 end
195 default: begin
196 data_d = 32'hBAAD_C0DE;
==>
197 end
198 endcase
199 state_d = Idle;
200 end
MISSING_ELSE
==>
201 end
202
203 Write: begin
204 dmi_req_valid = 1'b1;
205 // request sent, wait for response before going back to idle
206 if (dmi_req_ready) begin
-9-
207 state_d = WaitWriteValid;
==>
208 end
MISSING_ELSE
==>
209 end
210
211 WaitWriteValid: begin
212 // got a valid answer go back to idle
213 if (dmi_resp_valid) begin
-10-
214 unique case (dmi_resp.resp)
-11-
215 dm::DTM_ERR: error_dmi_op_failed = 1'b1;
==>
216 dm::DTM_BUSY: error_dmi_busy = 1'b1;
==>
217 default: ;
==>
218 endcase
219 state_d = Idle;
220 end
MISSING_ELSE
==>
221 end
222
223 default: begin
224 // just wait for idle here
225 if (dmi_resp_valid) begin
-12-
226 state_d = Idle;
==>
227 end
MISSING_ELSE
==>
228 end
229 endcase
230
231 // update means we got another request but we didn't finish
232 // the one in progress, this state is sticky
233 if (update && state_q != Idle) begin
-13-
234 error_dmi_busy = 1'b1;
==>
235 end
MISSING_ELSE
==>
236
237 // if capture goes high while we are in the read state
238 // or in the corresponding wait state we are not giving back a valid word
239 // -> throw an error
240 if (capture && state_q inside {Read, WaitReadValid}) begin
-14-
241 error_dmi_busy = 1'b1;
==>
242 end
MISSING_ELSE
==>
243
244 if (error_dmi_busy && error_q == DMINoError) begin
-15-
245 error_d = DMIBusy;
==>
246 end
MISSING_ELSE
==>
247
248 if (error_dmi_op_failed && error_q == DMINoError) begin
-16-
249 error_d = DMIOPFailed;
==>
250 end
MISSING_ELSE
==>
251
252 // clear sticky error flag
253 if (update && dtmcs_q.dmireset && dtmcs_select) begin
-17-
254 error_d = DMINoError;
==>
255 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Idle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Read |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Read |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_SUCCESS |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_ERR |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
DTM_BUSY |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T10,T11 |
| 0 |
WaitReadValid |
- |
- |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitReadValid |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Write |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
Write |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
DTM_ERR |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
DTM_BUSY |
- |
- |
- |
- |
- |
- |
Covered |
T3,T28,T29 |
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
1 |
default |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
WaitWriteValid |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T8,T74,T75 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T3,T28,T8 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Not Covered |
|
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T28,T8 |
| 0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
264 if (dmi_clear) begin
-1-
265 dr_d = '0;
==>
266 end else begin
267 if (capture) begin
-2-
268 if (dmi_select) begin
-3-
269 if (error_q == DMINoError && !error_dmi_busy) begin
-4-
270 dr_d = {address_q, data_q, DMINoError};
==>
271 // DMI was busy, report an error
272 end else if (error_q == DMIBusy || error_dmi_busy) begin
-5-
273 dr_d = {address_q, data_q, DMIBusy};
==>
274 end
MISSING_ELSE
==>
275 end
MISSING_ELSE
==>
276 end
MISSING_ELSE
==>
277
278 if (shift) begin
-6-
279 if (dmi_select) begin
-7-
280 dr_d = {tdi, dr_q[$bits(dr_q)-1:1]};
==>
281 end
MISSING_ELSE
==>
282 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
287 if (!trst_ni) begin
-1-
288 dr_q <= '0;
==>
289 state_q <= Idle;
290 address_q <= '0;
291 data_q <= '0;
292 error_q <= DMINoError;
293 end else begin
294 dr_q <= dr_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |