Unified Coverage Report :: Module :: dmi_cdc

Module : dmi_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_cdc	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.30	100.00	86.54			100.00	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.93	98.81	90.57		100.00	82.35		dap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_cdc_req	82.95	100.00	81.82			100.00	50.00
i_cdc_resp	83.93	100.00	85.71			100.00	50.00
u_combined_rstn_sync	100.00	100.00				100.00
u_rst_mux	100.00	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : dmi_cdc

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	121	1	1	100.00

54                        always_ff @(posedge tck_i or negedge trst_ni) begin
55         1/1              if (!trst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                jtag_combined_rstn <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (jtag_dmi_cdc_clear_i) begin
           Tests:       T1 T2 T3 
58         1/1                jtag_combined_rstn <= '0;
           Tests:       T1 T2 T3 
59                          end else begin
60         1/1                jtag_combined_rstn <= 1'b1;
           Tests:       T1 T2 T3 
61                          end
62                        end
63                      
64                        logic combined_rstn_premux;
65                        prim_flop_2sync #(
66                          .Width(1),
67                          .ResetValue(0)
68                        ) u_combined_rstn_sync (
69                          .clk_i,
70                          .rst_ni(rst_ni),
71                          .d_i(jtag_combined_rstn),
72                          .q_o(combined_rstn_premux)
73                        );
74                      
75                        logic combined_rstn;
76                        prim_clock_mux2 #(
77                          .NoFpgaBufG(1'b1)
78                        ) u_rst_mux (
79                          .clk0_i(combined_rstn_premux),
80                          .clk1_i(test_rst_ni),
81                          .sel_i(testmode_i),
82                          .clk_o(combined_rstn)
83                        );
84                      
85                        prim_fifo_async_simple #(
86                          .Width($bits(dm::dmi_req_t)),
87                          // Use the RZ protocol so that the two sides can be reset independently without getting
88                          // out of sync due to EVEN/ODD states.
89                          .EnRzHs(1)
90                        ) i_cdc_req (
91                          .clk_wr_i (tck_i),
92                          .rst_wr_ni(trst_ni),
93                          .wvalid_i (jtag_dmi_valid_i),
94                          .wready_o (jtag_dmi_ready_o),
95                          .wdata_i  (jtag_dmi_req_i),
96                          .clk_rd_i (clk_i),
97                          .rst_rd_ni(combined_rstn),
98                          .rvalid_o (core_dmi_valid_o),
99                          .rready_i (core_dmi_ready_i),
100                         .rdata_o  (core_dmi_req_o)
101                       );
102                     
103                       prim_fifo_async_simple #(
104                         .Width($bits(dm::dmi_resp_t)),
105                         // Use the RZ protocol so that the two sides can be reset independently without getting
106                         // out of sync due to EVEN/ODD states.
107                         .EnRzHs(1)
108                       ) i_cdc_resp (
109                         .clk_wr_i (clk_i),
110                         .rst_wr_ni(combined_rstn),
111                         .wvalid_i (core_dmi_valid_i),
112                         .wready_o (core_dmi_ready_o),
113                         .wdata_i  (core_dmi_resp_i),
114                         .clk_rd_i (tck_i),
115                         .rst_rd_ni(trst_ni),
116                         .rvalid_o (jtag_dmi_valid_o),
117                         .rready_i (jtag_dmi_ready_i),
118                         .rdata_o  (jtag_dmi_resp_o)
119                       );
120                     
121        1/1            assign core_dmi_rst_no = combined_rstn;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : dmi_cdc

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	55	3	3	100.00

55             if (!trst_ni) begin
               -1-  
56               jtag_combined_rstn <= '0;
                 ==>
57             end else if (jtag_dmi_cdc_clear_i) begin
                        -2-  
58               jtag_combined_rstn <= '0;
                 ==>
59             end else begin
60               jtag_combined_rstn <= 1'b1;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3