Unified Coverage Report :: Module :: prim_generic_and2

Module : prim_generic_and2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_blank_and

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_and2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i & in1_i;
           Tests:       T1 T2 T3