Module Definition
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Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_blank_and


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_and2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h.u_blank_and.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' or '../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1

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