Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9024411	9022983	0	0
selKnown1	106735310	106733882	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9024411	9022983	0	0
T1	11502	11500	0	0
T2	1772	1770	0	0
T3	1056	1054	0	0
T4	2608	2606	0	0
T5	650	646	0	0
T6	3	1	0	0
T7	0	2	0	0
T11	2012	2010	0	0
T12	2914	2912	0	0
T13	2	0	0	0
T18	30496	30494	0	0
T19	14846	14842	0	0
T20	2	0	0	0
T23	2	0	0	0
T37	2	0	0	0
T40	0	4	0	0
T41	0	10	0	0
T42	2	0	0	0
T43	2	0	0	0
T45	35021	35017	0	0
T48	0	12	0	0
T67	0	20	0	0
T71	0	20	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	106735310	106733882	0	0
T1	13338	13336	0	0
T2	7345	7343	0	0
T3	9172	9170	0	0
T4	3432	3430	0	0
T5	13805	13801	0	0
T6	2	0	0	0
T11	25504	25502	0	0
T12	91142	91140	0	0
T13	2	0	0	0
T18	118228	118226	0	0
T19	118670	118666	0	0
T20	2	0	0	0
T21	0	4	0	0
T23	2	0	0	0
T35	0	8	0	0
T37	2	0	0	0
T40	0	8	0	0
T41	0	10	0	0
T42	2	0	0	0
T43	2	0	0	0
T45	110366	110362	0	0
T48	0	8	0	0
T67	0	20	0	0
T71	0	40	0	0
T72	0	40	0	0
T77	0	40	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2925536	2925289	0	0
selKnown1	100636662	100636415	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925536	2925289	0	0
T1	5751	5750	0	0
T2	886	885	0	0
T3	528	527	0	0
T4	1304	1303	0	0
T5	324	323	0	0
T11	1006	1005	0	0
T12	1457	1456	0	0
T18	15248	15247	0	0
T19	7422	7421	0	0
T45	17505	17504	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	100636662	100636415	0	0
T1	7587	7586	0	0
T2	6459	6458	0	0
T3	8644	8643	0	0
T4	2128	2127	0	0
T5	13479	13478	0	0
T11	24498	24497	0	0
T12	89685	89684	0	0
T18	102980	102979	0	0
T19	111246	111245	0	0
T45	92851	92850	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	822	575	0	0
selKnown1	751	504	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	822	575	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	0	1	0	0
T13	1	0	0	0
T19	1	0	0	0
T20	1	0	0	0
T23	1	0	0	0
T37	1	0	0	0
T40	0	4	0	0
T41	0	5	0	0
T42	1	0	0	0
T43	1	0	0	0
T45	5	4	0	0
T48	0	5	0	0
T67	0	10	0	0
T71	0	20	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	751	504	0	0
T5	1	0	0	0
T6	1	0	0	0
T13	1	0	0	0
T19	1	0	0	0
T20	1	0	0	0
T21	0	2	0	0
T23	1	0	0	0
T35	0	4	0	0
T37	1	0	0	0
T40	0	4	0	0
T41	0	5	0	0
T42	1	0	0	0
T43	1	0	0	0
T45	5	4	0	0
T48	0	4	0	0
T67	0	10	0	0
T71	0	20	0	0
T72	0	20	0	0
T77	0	20	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6095929	6095462	0	0
selKnown1	6095929	6095462	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6095929	6095462	0	0
T1	5751	5750	0	0
T2	886	885	0	0
T3	528	527	0	0
T4	1304	1303	0	0
T5	324	323	0	0
T11	1006	1005	0	0
T12	1457	1456	0	0
T18	15248	15247	0	0
T19	7422	7421	0	0
T45	17505	17504	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	6095929	6095462	0	0
T1	5751	5750	0	0
T2	886	885	0	0
T3	528	527	0	0
T4	1304	1303	0	0
T5	324	323	0	0
T11	1006	1005	0	0
T12	1457	1456	0	0
T18	15248	15247	0	0
T19	7422	7421	0	0
T45	17505	17504	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2124	1657	0	0
selKnown1	1968	1501	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124	1657	0	0
T5	1	0	0	0
T6	2	1	0	0
T7	0	1	0	0
T13	1	0	0	0
T19	1	0	0	0
T20	1	0	0	0
T23	1	0	0	0
T37	1	0	0	0
T41	0	5	0	0
T42	1	0	0	0
T43	1	0	0	0
T45	6	5	0	0
T48	0	7	0	0
T67	0	10	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1968	1501	0	0
T5	1	0	0	0
T6	1	0	0	0
T13	1	0	0	0
T19	1	0	0	0
T20	1	0	0	0
T21	0	2	0	0
T23	1	0	0	0
T35	0	4	0	0
T37	1	0	0	0
T40	0	4	0	0
T41	0	5	0	0
T42	1	0	0	0
T43	1	0	0	0
T45	5	4	0	0
T48	0	4	0	0
T67	0	10	0	0
T71	0	20	0	0
T72	0	20	0	0
T77	0	20	0	0