Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9
1	1	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77,T27,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8114772	8113332	0	0
selKnown1	59202463	59201023	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8114772	8113332	0	0
T1	1568	1566	0	0
T2	2070	2068	0	0
T3	2812	2810	0	0
T6	874	870	0	0
T7	3	1	0	0
T8	4	2	0	0
T12	2818	2814	0	0
T17	1500	1498	0	0
T23	1302	1298	0	0
T26	2	0	0	0
T27	0	2	0	0
T28	2	0	0	0
T48	236	234	0	0
T49	5328	5324	0	0
T50	246	242	0	0
T51	0	2	0	0
T52	0	40	0	0
T74	0	1	0	0
T76	0	1	0	0
T77	3	1	0	0
T82	0	1	0	0
T104	0	40	0	0
T107	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	59202463	59201023	0	0
T1	11409	11407	0	0
T2	12147	12145	0	0
T3	28209	28207	0	0
T6	8568	8564	0	0
T7	2	0	0	0
T8	2	0	0	0
T9	0	8	0	0
T12	8878	8874	0	0
T17	20814	20812	0	0
T23	14930	14926	0	0
T26	2	0	0	0
T27	0	4	0	0
T28	2	0	0	0
T40	0	8	0	0
T48	6608	6606	0	0
T49	53243	53239	0	0
T50	3415	3411	0	0
T51	0	2	0	0
T52	0	40	0	0
T77	2	0	0	0
T82	0	2	0	0
T104	0	40	0	0
T108	0	20	0	0
T115	0	12	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9
1	1	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77,T27,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2480175	2479925	0	0
selKnown1	53568015	53567765	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2480175	2479925	0	0
T1	784	783	0	0
T2	1035	1034	0	0
T3	1406	1405	0	0
T6	435	434	0	0
T12	1408	1407	0	0
T17	750	749	0	0
T23	650	649	0	0
T48	118	117	0	0
T49	2643	2642	0	0
T50	122	121	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53567765	0	0
T1	10625	10624	0	0
T2	11112	11111	0	0
T3	26803	26802	0	0
T6	8131	8130	0	0
T12	7468	7467	0	0
T17	20064	20063	0	0
T23	14278	14277	0	0
T48	6490	6489	0	0
T49	50558	50557	0	0
T50	3291	3290	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T9,T44
1	1	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77,T27,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	757	507	0	0
selKnown1	720	470	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	757	507	0	0
T6	2	1	0	0
T7	1	0	0	0
T8	2	1	0	0
T12	1	0	0	0
T23	1	0	0	0
T26	1	0	0	0
T27	0	2	0	0
T28	1	0	0	0
T49	21	20	0	0
T50	1	0	0	0
T51	0	1	0	0
T52	0	20	0	0
T74	0	1	0	0
T77	1	0	0	0
T82	0	1	0	0
T104	0	20	0	0
T107	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	720	470	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	1	0	0	0
T9	0	4	0	0
T12	1	0	0	0
T23	1	0	0	0
T26	1	0	0	0
T27	0	2	0	0
T28	1	0	0	0
T40	0	4	0	0
T49	21	20	0	0
T50	1	0	0	0
T51	0	1	0	0
T52	0	20	0	0
T77	1	0	0	0
T82	0	1	0	0
T104	0	20	0	0
T108	0	10	0	0
T115	0	6	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9
1	1	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77,T27,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5632016	5631546	0	0
selKnown1	5632011	5631541	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5632016	5631546	0	0
T1	784	783	0	0
T2	1035	1034	0	0
T3	1406	1405	0	0
T6	435	434	0	0
T12	1408	1407	0	0
T17	750	749	0	0
T23	650	649	0	0
T48	118	117	0	0
T49	2643	2642	0	0
T50	122	121	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5632011	5631541	0	0
T1	784	783	0	0
T2	1035	1034	0	0
T3	1406	1405	0	0
T6	435	434	0	0
T12	1408	1407	0	0
T17	750	749	0	0
T23	650	649	0	0
T48	118	117	0	0
T49	2643	2642	0	0
T50	122	121	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T9,T44
1	1	Covered	T77,T27,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77,T27,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1824	1354	0	0
selKnown1	1717	1247	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1824	1354	0	0
T6	2	1	0	0
T7	2	1	0	0
T8	2	1	0	0
T12	1	0	0	0
T23	1	0	0	0
T26	1	0	0	0
T28	1	0	0	0
T49	21	20	0	0
T50	1	0	0	0
T51	0	1	0	0
T52	0	20	0	0
T76	0	1	0	0
T77	2	1	0	0
T104	0	20	0	0
T107	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717	1247	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	1	0	0	0
T9	0	4	0	0
T12	1	0	0	0
T23	1	0	0	0
T26	1	0	0	0
T27	0	2	0	0
T28	1	0	0	0
T40	0	4	0	0
T49	21	20	0	0
T50	1	0	0	0
T51	0	1	0	0
T52	0	20	0	0
T77	1	0	0	0
T82	0	1	0	0
T104	0	20	0	0
T108	0	10	0	0
T115	0	6	0	0