RV_TIMER Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	43.032m	429.193ms	192	200	96.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.660s	30.745us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	53.541us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.670s	721.018us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.880s	593.717us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.320s	27.769us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	53.541us	20	20	100.00
		rv_timer_csr_aliasing	0.880s	593.717us	5	5	100.00
V1		TOTAL			247	255	96.86
V2	random_reset	rv_timer_random_reset	20.809m	80.446ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.122m	681.141ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	18.135m	1.211s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	18.135m	1.211s	50	50	100.00
V2	stress	rv_timer_stress_all	1.287h	1.486s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	38.166us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.930s	727.655us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.930s	727.655us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.660s	30.745us	5	5	100.00
		rv_timer_csr_rw	0.610s	53.541us	20	20	100.00
		rv_timer_csr_aliasing	0.880s	593.717us	5	5	100.00
		rv_timer_same_csr_outstanding	0.780s	105.268us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.660s	30.745us	5	5	100.00
		rv_timer_csr_rw	0.610s	53.541us	20	20	100.00
		rv_timer_csr_aliasing	0.880s	593.717us	5	5	100.00
		rv_timer_same_csr_outstanding	0.780s	105.268us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	82.503us	5	5	100.00
		rv_timer_tl_intg_err	1.420s	112.928us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.420s	112.928us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	24.639m	119.705ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			610	620	98.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.38	98.73	100.00	--	100.00	100.00	99.89

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:

Test rv_timer_disabled has 1 failures.

10.rv_timer_disabled.2871836387
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random_reset has 1 failures.

31.rv_timer_random_reset.953004424
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random_reset/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random has 8 failures.

87.rv_timer_random.469884584
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/87.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

142.rv_timer_random.2214313388
Line 217, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/142.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.