RV_TIMER Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	45.926m	914.809ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.560s	50.438us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	15.153us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.830s	583.359us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.730s	18.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.750s	33.886us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	15.153us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	18.020us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	10.606m	69.335ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.285m	883.161ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	22.416m	1.305s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	22.416m	1.305s	50	50	100.00
V2	stress	rv_timer_stress_all	1.388h	1.476s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.600s	16.026us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.760s	337.855us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.760s	337.855us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.560s	50.438us	5	5	100.00
		rv_timer_csr_rw	0.610s	15.153us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	18.020us	5	5	100.00
		rv_timer_same_csr_outstanding	0.870s	38.876us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.560s	50.438us	5	5	100.00
		rv_timer_csr_rw	0.610s	15.153us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	18.020us	5	5	100.00
		rv_timer_same_csr_outstanding	0.870s	38.876us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.870s	88.495us	5	5	100.00
		rv_timer_tl_intg_err	1.360s	125.200us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.360s	125.200us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	25.346m	549.564ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			617	620	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.36	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
  • Test rv_timer_disabled has 3 failures.

    • 18.rv_timer_disabled.5171619505565283759420543773476583078538778440618409578655628726932911920078
      Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.rv_timer_disabled.99099827256140940397212684636657128776436254225197780775910183211071552551361
      Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

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