49a27e136c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 48.428m | 1.580s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 19.581us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 17.997us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.180s | 89.360us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 114.847us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.210s | 27.108us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 17.997us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 114.847us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 31.166m | 458.672ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.519m | 526.644ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 21.566m | 1.490s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 21.566m | 1.490s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.216h | 4.817s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 13.743us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.020s | 147.931us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.020s | 147.931us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 19.581us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 17.997us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 114.847us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 95.609us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 19.581us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 17.997us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 114.847us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 95.609us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 290 | 290 | 100.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.110s | 1.632ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.450s | 450.998us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.450s | 450.998us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 21.131m | 196.464ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 582 | 620 | 93.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 7 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.55 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.21 |
UVM_ERROR (cip_base_vseq.sv:774) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.24424503391046119499119956390369696931605021430666941544627065601532151085976
Line 1193, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72289258298 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 72289258298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.33779761670202531252645835715594644122346597700875018977148649458917633561498
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2868569986 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 2868569986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.