e0c4026501| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 36.843m | 164.411ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 20.384us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.660s | 29.271us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.190s | 91.950us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.800s | 117.608us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.560s | 67.167us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.660s | 29.271us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.800s | 117.608us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 30.669m | 219.514ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.359m | 226.810ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.720m | 3.581s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.720m | 3.581s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 50.431m | 1.977s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 40.818us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.130s | 398.311us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.130s | 398.311us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 20.384us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 29.271us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 117.608us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 136.065us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 20.384us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 29.271us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 117.608us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 136.065us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 952.110us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.360s | 124.823us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.360s | 124.823us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 19.950m | 645.966ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 577 | 620 | 93.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.57 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.32 |
UVM_ERROR (cip_base_vseq.sv:788) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
0.rv_timer_stress_all_with_rand_reset.2118871113819899228630631812395274746887806965537813372922861088122547623976
Line 328, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 49119927211 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10032 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 49119927211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.44450734274334877354421634956038580006910381545908155548836808187122044992311
Line 738, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50633302015 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 50633302015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rv_timer_random_reset has 1 failures.
10.rv_timer_random_reset.69386439510409077271948541207312380107036203217002922324236660242502471871985
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_disabled has 1 failures.
24.rv_timer_disabled.9736494630754351069196091366749107526459418821972550188682823985919796871439
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---