36c168c253| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 38.521m | 616.564ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 16.604us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.680s | 24.200us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.800s | 1.104ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.860s | 58.738us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.760s | 266.813us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.680s | 24.200us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.860s | 58.738us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 18.415m | 71.416ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.199m | 233.148ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.502m | 710.465ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.502m | 710.465ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 55.154m | 5.992s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 32.147us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.980s | 156.308us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.980s | 156.308us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 16.604us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.680s | 24.200us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 58.738us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.810s | 39.410us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 16.604us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.680s | 24.200us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 58.738us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.810s | 39.410us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 92.687us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.400s | 382.458us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.400s | 382.458us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 15.049m | 86.722ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
UVM_ERROR (cip_base_vseq.sv:827) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.31284193732980995987767392788290581590027880351070997645411772799353307004263
Line 867, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56249774318 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 56249774318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.70757385532356963798183676981607679447663725480641775018252433713664481277837
Line 344, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23011737337 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23011737337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
28.rv_timer_disabled.66890830846394519168816331689583539454060829726924378131687351535718953595364
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_timer_disabled.94333062833957553638797627402051899599691107363139187940800860919976291582660
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---