0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 46.602m | 520.157ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 43.537us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 31.133us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.410s | 1.839ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.780s | 263.718us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.520s | 110.385us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 31.133us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.780s | 263.718us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 23.569m | 108.978ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.909m | 828.983ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.611m | 1.805s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.611m | 1.805s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 49.706m | 2.796s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 27.871us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.870s | 227.167us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.870s | 227.167us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 43.537us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 31.133us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.780s | 263.718us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 82.134us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 43.537us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 31.133us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.780s | 263.718us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 82.134us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.170s | 259.513us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.550s | 973.216us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.550s | 973.216us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 20.090m | 597.585ms | 8 | 50 | 16.00 |
| V3 | TOTAL | 8 | 50 | 16.00 | |||
| TOTAL | 573 | 620 | 92.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:815) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:
0.rv_timer_stress_all_with_rand_reset.10152418182774138136069761247090100295474607067339006833973875046078126604441
Line 345, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29155544808 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29155544808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.36641075354131516217168652586777550790166953268266793767032319458683511009195
Line 378, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24075240140 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24075240140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
4.rv_timer_disabled.81397950048932718742701808376528957601671151750553740692636390539013031496846
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_timer_disabled.39458595546274603824383998187075228741827550718994970005855899967213283256597
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
80.rv_timer_random.52656337191807527237878912907959225136797657048834350150227577308304318076451
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/80.rv_timer_random/latest/run.log
Job ID: smart:af7ae39a-b30e-412b-aac1-e4cf750675a4