1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 200 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 255 | 0.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 50 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 50 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 290 | 0.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 5 | 0.00 | ||
| rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 620 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 7 | 7 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 620 failures:
0.rv_timer_random.12344719361131858489486627482824238738726465152508173309331922410034739586983
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
1.rv_timer_random.50302284383414259503934170042478381641150697040852736747003069677115967330300
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random/latest/run.log
... and 198 more failures.
0.rv_timer_disabled.94491155430531627474295800588949618314245947521018303499025621928369961949138
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
1.rv_timer_disabled.61362745924522090069334948863201828191408460832306092776073208735233661801610
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
... and 48 more failures.
0.rv_timer_cfg_update_on_fly.43371789921362498704345892989232194863989350046976261754975543063351012213481
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
1.rv_timer_cfg_update_on_fly.52578600639779945893898437847320805378318900931630333650770086010853970061800
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest/run.log
... and 48 more failures.
0.rv_timer_random_reset.29324474406448557323831521731926764211529942810550812065700645373706784443206
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
1.rv_timer_random_reset.99863357176348113225656218640510632377865546742323059213544777199328170784035
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
... and 48 more failures.
0.rv_timer_stress_all_with_rand_reset.67997782662647489221116705360726236875366999282237807904277911197026668449265
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
1.rv_timer_stress_all_with_rand_reset.27743979423974432923067748225973951712543341179318321902708031924653755013398
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/cov_report/cov_report.log