69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 47.125m | 154.775ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 14.708us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 51.742us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.960s | 1.634ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.730s | 160.549us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.470s | 35.611us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 51.742us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.730s | 160.549us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 43.338m | 482.595ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.157m | 910.534ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 27.711m | 1.664s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 27.711m | 1.664s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.729h | 5.844s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 15.558us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.850s | 113.572us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.850s | 113.572us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 14.708us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 51.742us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 160.549us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 141.354us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 14.708us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 51.742us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 160.549us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 141.354us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.970s | 332.037us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 129.784us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 129.784us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 27.306m | 152.442ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.52488083005772841687778411363343204132913656065892963850488442339383466666278
Line 602, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71806725610 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 71806725610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.113481581884489458709420558689357213822033498921599452105234148293834110057942
Line 639, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72730145418 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 72730145418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
0.rv_timer_disabled.41816742252185671713433101082460624106586541333091454352798947371836971836705
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_timer_disabled.64339568987022524040995833276557691009583419191116485792399024001028952087773
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
29.rv_timer_stress_all_with_rand_reset.59988111619937801033197214009299982005912880689159996367487554194709441607653
Line 307, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17199782338 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 17199782338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---