RV_TIMER Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	58.022m	873.999ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.650s	19.793us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.600s	35.097us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.590s	3.084ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.830s	54.835us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.590s	42.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.600s	35.097us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	54.835us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	31.523m	102.094ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.423m	1.000s	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	16.481m	561.233ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	16.481m	561.233ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.060h	1.348s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.610s	26.003us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.330s	1.429ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.330s	1.429ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.650s	19.793us	5	5	100.00
		rv_timer_csr_rw	0.600s	35.097us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	54.835us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	37.804us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.650s	19.793us	5	5	100.00
		rv_timer_csr_rw	0.600s	35.097us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	54.835us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	37.804us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.930s	426.553us	5	5	100.00
		rv_timer_tl_intg_err	1.430s	455.538us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s	455.538us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	24.664m	434.799ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			580	620	93.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.55	99.36	98.73	100.00	--	100.00	100.00	99.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rv_timer_stress_all_with_rand_reset has 35 failures.
  - 0.rv_timer_stress_all_with_rand_reset.87135339269663547440395709317460167241185606267224982974805046572826812903402
    Line 348, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 150149853354 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 150149853354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.29296398288691324455839105827818653613542568840947967991395244912705788415707
    Line 1829, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116212911209 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 116212911209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_disabled has 2 failures.
  - 3.rv_timer_disabled.1148197249996257940165310041651441762069018229575726613728456619835335845499
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.rv_timer_disabled.95767451160275246616023132129033849834012233290604315577778384153611473001603
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_stress_all has 1 failures.
  - 16.rv_timer_stress_all.75721731554642592661749199759748687541559955640390945991975729398013879093739
    Line 268, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 14.rv_timer_stress_all_with_rand_reset.57339713920108075772152668500086083332421748831446237892820353407084231130824
    Line 803, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 216327958078 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 216327958078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rv_timer_stress_all_with_rand_reset.70177388446595661328196123594604624405794506206612121374175485285925080781239
    Line 1152, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 434798941446 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 434798941446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `00fe426038`