349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 34.643m | 599.012ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 62.923us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 23.627us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.710s | 689.343us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.760s | 134.358us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.680s | 71.706us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 23.627us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.760s | 134.358us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 26.283m | 83.303ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.032m | 192.852ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 23.920m | 1.212s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 23.920m | 1.212s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 50.621m | 9.983s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 20.881us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.100s | 278.239us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.100s | 278.239us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 62.923us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 23.627us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 134.358us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 36.159us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 62.923us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 23.627us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 134.358us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 36.159us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.120s | 240.437us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 861.201us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 861.201us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 16.616m | 111.901ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
0.rv_timer_stress_all_with_rand_reset.53451432510098089264213359551192567529407471082376599188691037424942895312441
Line 702, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52087168203 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 52087168203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.72510529952843669459035375291241774111020661340976992225132744576029601237110
Line 429, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14605920192 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14605920192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
8.rv_timer_disabled.46566159047425376018388887054914231450555089895692457335917180296799294238935
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.rv_timer_disabled.19844668520373931318698813735341205933509477507984849940189241535170992551657
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---