RV_TIMER Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 34.643m 599.012ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.590s 62.923us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.620s 23.627us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.710s 689.343us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.760s 134.358us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.680s 71.706us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.620s 23.627us 20 20 100.00
rv_timer_csr_aliasing 0.760s 134.358us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 26.283m 83.303ms 50 50 100.00
V2 disabled rv_timer_disabled 5.032m 192.852ms 48 50 96.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 23.920m 1.212s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 23.920m 1.212s 50 50 100.00
V2 stress rv_timer_stress_all 50.621m 9.983s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.630s 20.881us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.100s 278.239us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.100s 278.239us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.590s 62.923us 5 5 100.00
rv_timer_csr_rw 0.620s 23.627us 20 20 100.00
rv_timer_csr_aliasing 0.760s 134.358us 5 5 100.00
rv_timer_same_csr_outstanding 0.870s 36.159us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.590s 62.923us 5 5 100.00
rv_timer_csr_rw 0.620s 23.627us 20 20 100.00
rv_timer_csr_aliasing 0.760s 134.358us 5 5 100.00
rv_timer_same_csr_outstanding 0.870s 36.159us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err rv_timer_sec_cm 1.120s 240.437us 5 5 100.00
rv_timer_tl_intg_err 1.410s 861.201us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.410s 861.201us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 16.616m 111.901ms 13 50 26.00
V3 TOTAL 13 50 26.00
TOTAL 581 620 93.71

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.51 99.36 98.73 100.00 -- 100.00 100.00 98.98

Failure Buckets

Past Results