RV_TIMER Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	59.106m	557.629ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.640s	38.635us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.640s	47.687us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.590s	1.493ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.800s	87.666us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.530s	130.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.640s	47.687us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	87.666us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	14.113m	44.002ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.583m	202.249ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	23.384m	4.223s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	23.384m	4.223s	50	50	100.00
V2	stress	rv_timer_stress_all	1.958h	1.483s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.620s	31.313us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.120s	148.562us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.120s	148.562us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.640s	38.635us	5	5	100.00
		rv_timer_csr_rw	0.640s	47.687us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	87.666us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	116.149us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.640s	38.635us	5	5	100.00
		rv_timer_csr_rw	0.640s	47.687us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	87.666us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	116.149us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	1.270s	385.040us	5	5	100.00
		rv_timer_tl_intg_err	1.490s	123.738us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.490s	123.738us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.557m	159.901ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			576	620	92.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	4	57.14
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.55	99.36	98.73	100.00	--	100.00	100.00	99.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
- Test rv_timer_stress_all_with_rand_reset has 39 failures.
  - 0.rv_timer_stress_all_with_rand_reset.57433088872109612619471526080527957651076468955623097235887061611869190839342
    Line 668, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78254654321 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10025 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 78254654321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.36243582915035397769224686892696666273683090203825695607660622810078714853682
    Line 395, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34038721322 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34038721322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 37 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_timer_disabled has 2 failures.
  - 9.rv_timer_disabled.78752566263403564450102987992718737196014569626831509104224647434138231590183
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.rv_timer_disabled.16968222505972629218389823970264825933687208578547118546717208932590110410111
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_stress_all has 1 failures.
  - 22.rv_timer_stress_all.102936468758237473517053711105170067077287328304360411037529087615218248419995
    Line 273, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 33.rv_timer_random_reset.62538527627970262073307455772536789658557957935494510473601237592073833581505
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 42.rv_timer_random.97363212903700093472524490888850382880066381466248387765888088874230098927796
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_random/latest/run.log
```
  Job ID: smart:b36cf2e7-832d-4f15-a830-c51a2cdaca41
```

RV_TIMER Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be3d980075`