RV_TIMER Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 54.740m 736.286ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.630s 194.624us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.640s 24.635us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.570s 1.111ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.740s 18.392us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.380s 104.455us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.640s 24.635us 20 20 100.00
rv_timer_csr_aliasing 0.740s 18.392us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 14.330m 94.212ms 50 50 100.00
V2 disabled rv_timer_disabled 6.099m 808.635ms 46 50 92.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 19.496m 2.119s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 19.496m 2.119s 50 50 100.00
V2 stress rv_timer_stress_all 1.350h 393.965ms 50 50 100.00
V2 intr_test rv_timer_intr_test 0.620s 11.524us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.360s 177.169us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.360s 177.169us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.630s 194.624us 5 5 100.00
rv_timer_csr_rw 0.640s 24.635us 20 20 100.00
rv_timer_csr_aliasing 0.740s 18.392us 5 5 100.00
rv_timer_same_csr_outstanding 0.860s 126.203us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.630s 194.624us 5 5 100.00
rv_timer_csr_rw 0.640s 24.635us 20 20 100.00
rv_timer_csr_aliasing 0.740s 18.392us 5 5 100.00
rv_timer_same_csr_outstanding 0.860s 126.203us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err rv_timer_sec_cm 0.990s 139.262us 5 5 100.00
rv_timer_tl_intg_err 1.540s 525.624us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.540s 525.624us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 24.355m 391.511ms 12 50 24.00
V3 TOTAL 12 50 24.00
TOTAL 578 620 93.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.61 99.36 98.73 100.00 -- 100.00 100.00 99.55

Failure Buckets

Past Results