RV_TIMER Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	33.624m	178.524ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.570s	24.285us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.630s	15.077us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.560s	2.383ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	31.850us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.760s	72.803us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.630s	15.077us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	31.850us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	30.279m	61.978ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.403m	504.125ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.567m	5.259s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.567m	5.259s	50	50	100.00
V2	stress	rv_timer_stress_all	53.566m	10.000s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.600s	57.053us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.230s	767.818us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.230s	767.818us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.570s	24.285us	5	5	100.00
		rv_timer_csr_rw	0.630s	15.077us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	31.850us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	22.883us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.570s	24.285us	5	5	100.00
		rv_timer_csr_rw	0.630s	15.077us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	31.850us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	22.883us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	0.930s	167.004us	5	5	100.00
		rv_timer_tl_intg_err	1.410s	518.408us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.410s	518.408us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	19.172m	105.089ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			577	620	93.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.36	98.73	100.00	--	100.00	100.00	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test rv_timer_stress_all_with_rand_reset has 36 failures.
  - 0.rv_timer_stress_all_with_rand_reset.47913584617612250435814150137881560408945321692322599218292433470878429070592
    Line 492, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81250557956 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10013 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 81250557956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.71149369172609208968471136344740462963833615046770567302483769190726024989984
    Line 509, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44082360351 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10038 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 44082360351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_timer_disabled has 3 failures.
  - 5.rv_timer_disabled.65243139700159750573706299256028619726957710590517254300541956179550026838346
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rv_timer_disabled.24110622592846006368342196518323665812273720154890074588153174227158161370719
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test rv_timer_stress_all has 1 failures.
  - 7.rv_timer_stress_all.104822235162079020008712285003638427137534647467938274021624911733736503688339
    Line 283, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 3.rv_timer_stress_all_with_rand_reset.55723798975032415816524746383104627515093321142682033448252765601270421819426
    Line 269, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6886743957 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6886743957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.rv_timer_stress_all_with_rand_reset.39739789267226026779565839792001098124705249129276099647921434305237480816930
    Line 772, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45067117419 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 45067117419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 171.rv_timer_random.101512870347172739083457170938043447816459724975411848255251850611542995742159
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/171.rv_timer_random/latest/run.log
```
  Job ID: smart:a89d4666-be2f-41df-9b63-438a05282546
```

RV_TIMER Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0e5093d709`