3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 55.883m | 1.706s | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 19.250us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 24.065us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.660s | 3.030ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 18.910us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.690s | 32.674us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 24.065us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 18.910us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 28.164m | 95.527ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.891m | 408.970ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 22.882m | 1.512s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 22.882m | 1.512s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.430h | 2.707s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 23.063us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.480s | 360.983us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.480s | 360.983us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 19.250us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 24.065us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 18.910us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.880s | 70.837us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 19.250us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 24.065us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 18.910us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.880s | 70.837us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.890s | 79.173us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 112.617us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 112.617us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 33.491m | 55.563ms | 8 | 50 | 16.00 |
| V3 | TOTAL | 8 | 50 | 16.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
3.rv_timer_stress_all_with_rand_reset.24953277821896441989217959129748271945797298165819850660632020325574724522946
Line 555, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 289377753970 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10028 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 289377753970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_timer_stress_all_with_rand_reset.7548432291427436619392281889221283109229420739955381709478697638235344340002
Line 437, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 54141388643 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10076 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 54141388643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
13.rv_timer_stress_all_with_rand_reset.18172004795312103462755334219203991047282028303033717199716867796230213398
Line 347, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26855206563 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 26855206563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
38.rv_timer_disabled.75383565253696732672033791367833477615511927770436119381391956731701394384818
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
77.rv_timer_random.80017377459527024233173806868325771995875260395919094485670622352448864286541
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/77.rv_timer_random/latest/run.log
Job ID: smart:8616b3b1-0c7b-43fd-bc77-b3abc0a8f8eb