b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 41.584m | 1.980s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 46.951us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 14.490us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.700s | 2.402ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.780s | 20.775us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.570s | 130.810us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 14.490us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.780s | 20.775us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 31.297m | 149.183ms | 48 | 50 | 96.00 |
| V2 | disabled | rv_timer_disabled | 5.219m | 699.379ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 35.813m | 8.359s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 35.813m | 8.359s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.144h | 8.431s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 55.571us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.070s | 177.547us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.070s | 177.547us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 46.951us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 14.490us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.780s | 20.775us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 20.170us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 46.951us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 14.490us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.780s | 20.775us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 20.170us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.930s | 909.148us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.390s | 2.375ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.390s | 2.375ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 28.817m | 511.134ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
0.rv_timer_stress_all_with_rand_reset.100933305403130901270405754826663172096540665907385259182070701890922319396807
Line 1035, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 88252996362 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 88252996362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.96709877572138188815001666797789826458564201239803551481540780178960152625635
Line 2103, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 142416725422 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10023 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 142416725422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
27.rv_timer_random_reset.89328284241717444973249677051117746732272615413631408268265197156293002920666
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.rv_timer_random_reset.27131275880094390953312900063969873943918781293022313555826123873018937940976
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---